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IEEE Transactions on Information Forensics and Security

Issue 1  Part 1 • Feb. 2012

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  • Table of contents

    Publication Year: 2012, Page(s): C1
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  • IEEE Transactions on Information Forensics and Security publication information

    Publication Year: 2012, Page(s): C2
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  • Guest Editorial - Integrated Circuit and System Security

    Publication Year: 2012, Page(s):1 - 2
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  • A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits

    Publication Year: 2012, Page(s):3 - 13
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2730 KB) | HTML iconHTML

    This paper proposes a formal approach to designing Galois-field (GF) arithmetic circuits, which are widely used in modern cryptographic processors. Our method describes GF arithmetic circuits in a hierarchical manner with high-level directed graphs associated with specific GFs and arithmetic functions. The proposed circuit description can be effectively verified by symbolic computations based on p... View full abstract»

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  • Intrinsic Physical-Layer Authentication of Integrated Circuits

    Publication Year: 2012, Page(s):14 - 24
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1917 KB) | HTML iconHTML

    Radio-frequency distinct native attribute (RF-DNA) fingerprinting is adapted as a physical-layer technique to improve the security of integrated circuit (IC)-based multifactor authentication systems. Device recognition tasks (both identification and verification) are accomplished by passively monitoring and exploiting the intrinsic features of an IC's unintentional RF emissions without requiring a... View full abstract»

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  • Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition

    Publication Year: 2012, Page(s):25 - 40
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB) | HTML iconHTML

    We present a novel framework for facilitating the acquisition of provably trustworthy hardware intellectual property (IP). The proposed framework draws upon research in the field of proof-carrying code (PCC) to allow for formal yet computationally straightforward validation of security-related properties by the IP consumer. These security-related properties, agreed upon a priori by the IP vendor a... View full abstract»

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  • Improved Differential Fault Analysis on AES Key Schedule

    Publication Year: 2012, Page(s):41 - 50
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2929 KB) | HTML iconHTML

    Differential fault analysis (DFA) finds the key of a block cipher using differential information between correct and faulty ciphertexts obtained by inducing faults during the computation of ciphertexts. Among many ciphers, advanced encryption standard (AES) has been the main target of DFA due to its popularity. The naive implementation of AES is known to be vulnerable to DFA, which can be split in... View full abstract»

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  • Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management

    Publication Year: 2012, Page(s):51 - 63
    Cited by:  Papers (47)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1254 KB) | HTML iconHTML

    In the horizontal semiconductor business model where the designer's intellectual property (IP) is transparent to foundry and to other entities on the production chain, integrated circuits (ICs) overbuilding and IP piracy are prevalent problems. Active metering is a suite of methods enabling the designers to control their chips postfabrication. We provide a comprehensive description of the first kn... View full abstract»

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  • Characterizing the Efficacy of the NRL Network Pump in Mitigating Covert Timing Channels

    Publication Year: 2012, Page(s):64 - 75
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2453 KB) | HTML iconHTML

    The Naval Research Laboratory (NRL) Network Pump, or Pump, is a standard for mitigating covert channels that arise in a multilevel secure (MLS) system when a high user (HU) sends acknowledgements to a low user (LU). The issue here is that HU can encode information in the "timings" of the acknowledgements. The Pump aims at mitigating the covert timing channel by introducing buffering between HU and... View full abstract»

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  • Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection

    Publication Year: 2012, Page(s):76 - 87
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1732 KB) | HTML iconHTML

    Government agencies and the semiconductor industry have raised serious concerns about malicious modifications to the integrated circuits. The added functionality known as hardware Trojan poses major detection and isolation challenges. This paper presents a new hardware trust architecture to magnify functional Trojans activity. Trojan detection resolution depends on Trojan activity directly and cir... View full abstract»

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  • New Fault-Based Side-Channel Attack Using Fault Sensitivity

    Publication Year: 2012, Page(s):88 - 97
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1680 KB) | HTML iconHTML

    This paper proposes a new fault-based attack called fault sensitivity analysis (FSA) attack. In the FSA attack, fault injections are used to test out the sensitive information leakage called fault sensitivity. Fault sensitivity means the critical fault injection intensity that corresponds to the threshold between devices' normal and abnormal behaviors. We demonstrate that without using the values ... View full abstract»

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  • A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

    Publication Year: 2012, Page(s):98 - 108
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB) | HTML iconHTML

    Currently achievable intellectual property (IP) protection solutions for field-programmable gate arrays (FPGAs) are limited to single large "monolithic" configurations. However, the ever growing capabilities of FPGAs and the consequential increasing complexity of their designs ask for a modular development model, where individual IP cores from multiple parties are integrated into a larger system. ... View full abstract»

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  • Information-Theoretic Approach to Optimal Differential Fault Analysis

    Publication Year: 2012, Page(s):109 - 120
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1910 KB) | HTML iconHTML

    This paper presents a comprehensive analysis of differential fault analysis (DFA) attacks on the Advanced Encryption Standard (AES) from an information-theoretic perspective. Injecting faults into cryptosystems is categorized as an active at tack where attackers induce an error in operations to retrieve the secret internal information, e.g., the secret key of ciphers. Here, we consider DFA attacks... View full abstract»

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  • IEEE Transactions on Information Forensics and Security Edics

    Publication Year: 2012, Page(s): 121
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  • IEEE Transactions on Information Forensics and Security information for authors

    Publication Year: 2012, Page(s):122 - 123
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  • Renew your IEEE membership for 2012 and add Signal Processing Society [advertisement]

    Publication Year: 2012, Page(s): 124
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  • IEEE Signal Processing Society Information

    Publication Year: 2012, Page(s): C3
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    Publication Year: 2012, Page(s): C4
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Aims & Scope

The IEEE Transactions on Information Forensics and Security covers the sciences, technologies, and applications relating to information forensics, information security, biometrics, surveillance and systems applications that incorporate these features.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Mauro Barni
University of Siena, Italy