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Display Technology, Journal of

Issue 1 • Date Jan. 2012

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Displaying Results 1 - 20 of 20
  • [Front cover]

    Publication Year: 2012 , Page(s): C1
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  • Journal of Display Technology publication information

    Publication Year: 2012 , Page(s): C2
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  • Table of contents

    Publication Year: 2012 , Page(s): 1
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  • Blank page

    Publication Year: 2012 , Page(s): 2
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  • The Inventors of TFT Active-Matrix LCD Receive the 2011 IEEE Nishizawa Medal

    Publication Year: 2012 , Page(s): 3 - 4
    Cited by:  Papers (1)
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  • Guest Editorial

    Publication Year: 2012 , Page(s): 5 - 6
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  • Integrated a-Si:H Source Driver With Improved Output Voltage for e-Paper

    Publication Year: 2012 , Page(s): 7 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (729 KB) |  | HTML iconHTML  

    A hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) source driver for e-paper was designed with a latch and bootstrap selection circuit. The source driver was optimized by simulation and verified with measurements after circuit fabrication. The output waveforms of the conventional and proposed a-Si:H source drivers were compared. The proposed a-Si:H TFT source driver provided a shorter rise time and higher output voltages than the conventional one. View full abstract»

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  • Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

    Publication Year: 2012 , Page(s): 12 - 17
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    In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage VTH from 10.87 V to 5.00 V. Moreover, the threshold voltage VTH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density Nt. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility μFE. Therefore, the channel length dependence of field-effect mobility μFE is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect. View full abstract»

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  • Reduction of Short Channel Effects and Hot Carrier Induced Instability in Fully Self-Aligned Gate Overlapped Lightly Doped Drain Polysilicon TFTs

    Publication Year: 2012 , Page(s): 18 - 22
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 1012 cm2. View full abstract»

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  • Mechanisms of Threshold Voltage Shift in Polymorphous and Microcrystalline Silicon Bottom Gate Thin-Film Transistors

    Publication Year: 2012 , Page(s): 23 - 26
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    In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and μc-Si:F:H bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with ΔVTH=1 V after 10 h of stress and μc-Si:F:H TFTs with superior stability, which show a ΔVTH of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime (VG=12 V and VD=10 V). Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or μc-Si:F:H) controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface. View full abstract»

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  • Electrical Stability of High-Mobility Microcrystalline Silicon Thin-Film Transistors

    Publication Year: 2012 , Page(s): 27 - 34
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    The electrical stability of high-mobility microcrystalline silicon (μc -Si:H) thin-film transistors (TFTs) was investigated and compared to amorphous silicon (a-Si:H) TFTs. Under prolonged bias stress the microcrystalline silicon TFTs exhibit an improved electrical stability compared to amorphous silicon TFTs. The microcrystalline silicon TFTs were prepared by plasma-enhanced chemical vapor deposition at temperatures compatible with flexible substrates. The realized microcrystalline silicon transistors exhibit electron charge carrier mobilities exceeding 30 cm2/V·s. Prolonged operation of the transistors leads to a shift of the threshold voltage towards positive and negative gate voltages depending on the gate biasing conditions (positive or negative gate voltage). The shift of the threshold voltage increases with increasing positive and negative gate bias stress. The behavior is fundamentally different from the behavior of the amorphous silicon TFTs, which exhibit only a shift of the threshold voltage towards positive gate voltages irrespective of the polarity of the gate bias stress. The threshold voltage shift of the microcrystalline silicon TFTs saturates after a few minutes to a few hours, depending on the gate voltage. After prolonged bias stress, a recovery of the initial threshold voltage is observed without any thermal annealing or biasing of the transistors, which is not the case for the measured amorphous silicon TFTs. View full abstract»

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  • Effect of Self-Assembled Monolayer (SAM) on the Oxide Semiconductor Thin Film Transistor

    Publication Year: 2012 , Page(s): 35 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    In this paper, we proposed the self-assembled monolayer (SAM) as a protection layer against plasma and chemically induced damages to the back interface of an oxide semiconductor during the deposition of the passivation layer. When a thin-film transistor (TFT) is passivated with plasma-enhanced chemical-vapor deposition (PECVD) SiOx and solution-based materials, the back interface of the oxide semiconductor could be exposed to plasma and chemically induced damages, respectively. We employed SAMs on the back surface of the oxide semiconductor prior to the passivation process to suppress such damage. The hydrophobic Cl-SAM (3-chloropropyltriethoxysilane) suppressed the degradation in mobility and subthreshold slope (SS) due to ion bombardment during plasma treatment. The hydrophobic CH3-SAM (octyltriethoxysilane) successfully blocked chemically induced damage due to solution-based passivation. View full abstract»

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  • p-Type {\hbox {Cu}}_{x}{\hbox {O}} Films Deposited at Room Temperature for Thin-Film Transistors

    Publication Year: 2012 , Page(s): 41 - 47
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1210 KB) |  | HTML iconHTML  

    Thin-films of copper oxide (CuxO) were sputtered from a metallic copper (Cu) target and studied as a function of oxygen partial pressure (OPP). A metallic Cu film with cubic structure obtained from 0% OPP has been transformed to cubic Cu2O phase for the increase in OPP to 9% but then changed to monoclinic CuO phase (for OPP ≥ 25%). The variation in crystallite size (calculated from x-ray diffraction data) was further substantiated by the variation in grain size (surface microstructures). The CuxO films produced with OPP ranging between 9% and 75% showed p-type behavior, which were successfully applied to produce thin-film transistors. View full abstract»

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  • Contact Resistance of Inkjet-Printed Silver Source–Drain Electrodes in Bottom-Contact OTFTs

    Publication Year: 2012 , Page(s): 48 - 53
    Cited by:  Papers (3)
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    In this paper, we report contact resistance analysis between inkjet-printed silver source-drain (S/D) electrodes and organic semiconductor layer in bottom-contact organic thin-film transistors (OTFTs) using transmission line method (TLM). Inkjet-printed silver electrodes, spin-coated PVP and evaporated pentacene were used as gate and S/D electrodes, gate dielectric layer and semiconductor layer, respectively. On a common gate electrode, S/D electrodes with various channel length from 15 to 111 μm were printed for TLM analysis. The same bottom-contact OTFT with evaporated silver S/D electrodes was also fabricated for reference. We extracted contact resistances of 1.79 MΩ·cm and 0.55 MΩ·cm for inkjet-printed and evaporated silver electrodes, respectively. Higher contact resistance for inkjet-printed silver electrodes can be explained in terms of their relatively poor surface properties at electrode edge that can cause small pentacene molecule grain or slight oxidation of surface during the printed silver sintering process. View full abstract»

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  • Thin-Film Transistors and Circuits Based on Carbon Nanotubes

    Publication Year: 2012 , Page(s): 54 - 60
    Cited by:  Patents (1)
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    Carbon nanotubes are actively studied for thin-film transistor and electronics applications. Although these nanomaterials were first considered as potential candidates for the replacement of Si MOS type transistors in VLSI circuits, their main field of application is shifting towards large area electronics on flexible, plastic-type substrates, a domain which is at present, less demanding in terms of device dimensions and integration density. In particular, random networks of carbon nanotubes, which can be obtained by solution-processing or grown at low temperature, represent an attractive and viable option for the fabrication of electronic circuitry on non-refractory substrates. This paper briefly reviews some recent advances in the field, highlighting realisations beyond the fabrication of simple transistors. View full abstract»

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  • Blank page

    Publication Year: 2012 , Page(s): 61 - 62
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  • Special issue on From 100G to Terabit Optical Networking

    Publication Year: 2012 , Page(s): 63
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  • Special issue on nanoplasmonics

    Publication Year: 2012 , Page(s): 64
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  • Journal of Display Technology information for authors

    Publication Year: 2012 , Page(s): C3
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  • Blank page [back cover]

    Publication Year: 2012 , Page(s): C4
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Aims & Scope

This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Arokia Nathan
University of Cambridge
Cambridge, U.K.