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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Dec. 1988

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Displaying Results 1 - 9 of 9
  • SPIDER: capacitance modelling for VLSI interconnections

    Publication Year: 1988, Page(s):1221 - 1228
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (642 KB)

    An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form ... View full abstract»

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  • MOSTSM: a physically based charge conservative MOSFET model

    Publication Year: 1988, Page(s):1229 - 1236
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (623 KB)

    Charge-conservative CV models for the MOSFET can be classified into two categories: a depletion charge model, which is accurate but complex, and a simplified charge model, which is less accurate but is very simple. The accuracy of the latter model is investigated. The model error of C/sub BD/ and C/sub BS/ is found to be between 10 and 26 percent even in a long-channel MOSFET. The model of the bul... View full abstract»

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  • Macromodeling CMOS circuits for timing simulation

    Publication Year: 1988, Page(s):1237 - 1249
    Cited by:  Papers (47)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1305 KB)

    A macromodeling and timing simulation technique is presented that allows fast and accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. Typical delay times were within 5% for lo... View full abstract»

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  • A concurrent testing technique for digital circuits

    Publication Year: 1988, Page(s):1250 - 1260
    Cited by:  Papers (55)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (895 KB)

    A method is presented for testing digital circuits during normal operation. The resources used to perform online testing are those which are inserted to alleviate the offline testing problem. The offline testing resources are modified so that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to the circuit under tes... View full abstract»

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  • MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

    Publication Year: 1988, Page(s):1290 - 1300
    Cited by:  Papers (179)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1108 KB)

    The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multileve... View full abstract»

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  • A macrocell approach for VLSI processor design

    Publication Year: 1988, Page(s):1272 - 1277
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    An effective layout design method for VLSI processors, called the `macrocell approach' is presented. The approach bridges the gap between full manual layout and polycell/standard cell layout with respect to the design productivity and the performance. After precise floorplanning, functional blocks are designed into macrocells using a flexible symbolic layout method, and a VLSI chip is laid out by ... View full abstract»

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  • Implementation of VLSI self-testing by regularization

    Publication Year: 1988, Page(s):1261 - 1271
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    A novel circuit design methodology is developed for comprehensive offline self-testing of nearly regular VLSI circuits. It is based on four major design techniques: circuit partitioning, regularization to produce identical subcircuits (modules), parallel testing of modules, and fault detection by direct comparison of response streams from the modules. A generalization of I-testing called sequentia... View full abstract»

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  • Algorithms for floorplan design via rectangular dualization

    Publication Year: 1988, Page(s):1278 - 1289
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1044 KB)

    A rectangular floorplan construction problem is approached from a graph-theoretical view. The study is based on a reduction of the rectangular dualization problem to a matching problem on bipartite graphs. This opens the way to applying traditional graph-theoretic methods and algorithms to floorplanning. Another result is a method for generating alternative rectangular duals, such that a proposed ... View full abstract»

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  • An improved Spice2 Zener diode model for soft-region simulation capability

    Publication Year: 1988, Page(s):1301 - 1303
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    A Spice2-compatible reverse diode model is formulated in which improvements are made to reverse low current leakage region. In addition, the diode parasitic series resistance is included in the breakdown region of the model and forces the model parameters IBV and BV to describe the terminal characteristics, as opposed to the internal diode component as in Spice2. The proposed mo... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu