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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 12 • Date Dec. 2011

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Displaying Results 1 - 25 of 36
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2011 , Page(s): C2
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  • Introduction to the Special Section on Energy-Harvesting/Scavenging Circuits and Systems

    Publication Year: 2011 , Page(s): 785 - 786
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  • Increasing Electrical Damping in Energy-Harnessing Transducers

    Publication Year: 2011 , Page(s): 787 - 791
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    Wireless microsensors that monitor and detect activity in factories, farms, military camps, vehicles, hospitals, and the human body can save money, energy, and lives. Miniaturized batteries, unfortunately, easily exhaust, which limit deployment to few niche markets. Luckily, harnessing ambient energy offers hope. The challenge is tiny transducers convert only a small fraction of the energy available into the electrical domain, and the microelectronics that transfer and condition power dissipate some of that energy, further reducing the budget on which microsystems rely to operate. Improving transducers and trimming power losses in the system to increase output power is therefore of paramount importance. Increasing the electrical damping force against which transducers work also deserves attention because output power is, fundamentally, the result of damping. This paper explores how investing energy to increase electrical damping can boost output power in electromagnetic, electrostatic, and piezoelectric transducers. View full abstract»

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  • Tuning the Resonant Frequency and Damping of an Electromagnetic Energy Harvester Using Power Electronics

    Publication Year: 2011 , Page(s): 792 - 796
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (553 KB) |  | HTML iconHTML  

    In order to maximize power density, the resonant frequency of an energy harvester should be equal to the source excitation frequency and the electrical damping set equal to the parasitic damping. These parameters should be adjustable during device operation because the excitation characteristics can change. This brief presents, for the first time, a power electronic interface that is capable of continual adjustment of the damping and the resonant frequency of an energy harvester by controlling real and reactive power exchange between the electrical and mechanical domains while storing the harvested energy in a battery. The advantages of this technique over previously proposed methods are the precise control over the tuning parameters of the electrical system and integrated rectification within the tuning interface. Experimental results verify the operation, and the prototype system presented can change the resonant frequency of the electromechanical system by ±10% and increase the damping by 45%. As the input excitation frequency was swept away from the unmodified resonant frequency of the harvester, the use of the tuning mechanism was shown to increase real power generation by up to 25%. The prototype harvester is capable of generating 100 mW at an excitation frequency of 1.25 Hz. View full abstract»

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  • The Doubler of Electricity Used as Battery Charger

    Publication Year: 2011 , Page(s): 797 - 801
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    This brief describes several ways in which a variation of the electrostatic generator known as “doubler of electricity” or “Bennet's doubler” can be used as a practical micropower generator and a battery charger. The device has a structure that can be constructed as a microelectromechanical system device powered by ambient vibration. A simple battery charger that does not require any control circuit for operation is detailed, and the inherent instability of the device is exploited to allow greater power output, with experimental results presented. View full abstract»

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  • A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting

    Publication Year: 2011 , Page(s): 802 - 806
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    This brief presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450 nW; thus, the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions. View full abstract»

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  • Photovoltaic Antennas for Autonomous Wireless Systems

    Publication Year: 2011 , Page(s): 807 - 811
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    Photovoltaic (PV) antennas are used as both direct-current power source and radio-frequency radiator or receptor, resulting in a smarter integrated wireless system. Antenna designs and power management schemes for outdoor and indoor environments are proposed and compared. A dipole and a loop antenna based on amorphous-silicon PV cells were designed for 3.1-10.6 GHz ultrawideband communications. The harvested light energy is either stored in a supercapacitor or a rechargeable battery to ensure system autonomy. Both antenna prototypes are implemented in wireless sensor nodes, which transmit data packets every 8.5 s at 10 kb/s. View full abstract»

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  • A Temperature and Process Compensated Ultralow-Voltage Rectifier in Standard Threshold CMOS for Energy-Harvesting Applications

    Publication Year: 2011 , Page(s): 812 - 816
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (533 KB) |  | HTML iconHTML  

    This brief presents an ultralow-voltage multistage rectifier built with standard threshold CMOS for energy-harvesting applications. A threshold-compensated diode (TCD) is developed to minimize the forward voltage drop while maintaining low reverse leakage flow. In addition, an interstage compensation scheme is proposed that enables efficient power conversion at input amplitudes below the diode threshold. The new rectifier also features an inherent temperature and process compensation mechanism, which is achieved by precisely tracking the diode threshold by an auxiliary dummy. Although the design is optimized for an ac input at 13.56 MHz, the presented enhancement techniques are also applicable for low- or ultrahigh-frequency energy scavengers. The rectifier prototype is fabricated in a 0.35-μm four-metal two-poly standard CMOS process with the worst-case threshold voltage of 600 mV/- 780 mV for nMOS/pMOS, respectively. With a 13.56 MHz input of a 500 mV amplitude, the rectifier is able to deliver more than 35 μW at 2.5 V VDD, and the measured deviation in the output voltage is as low as 180 mV over 100°C for a cascade of ten TCDs. View full abstract»

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  • Subnanosecond Pulse Generators for Impulsive Wireless Power Transmission and Reception

    Publication Year: 2011 , Page(s): 817 - 821
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    This brief describes a novel impulsive wireless power transmission (WPT) and reception system. This new concept enhances the power conversion efficiency (PCE) for low average input power. Low input power is important in several applications, such as biomedical implant devices and energy harvesting from unknown sources. An ultrawideband (UWB) monocycle pulse generator is designed using a shunt step recovery diode. The fabricated pulse generator produces an impulse width of approximately 290 ps. Complete wideband transmitting and receiving systems are implemented to validate the feasibility of impulsive WPT technologies and to assess the improvement of the conversion efficiency of the rectifier circuitry. Finally, UWB impulsive wireless transmission systems demonstrate 59.6% PCE, even when the input power of the rectifier is less than - 2.84 dBm. View full abstract»

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  • Far-Field RF-Powered Variable Duty Cycle Wireless Sensor Platform

    Publication Year: 2011 , Page(s): 822 - 826
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    This brief discusses a low-power wireless sensor based on commercial components for sensing and data transmission. The sensor is wirelessly powered from the far field through an integrated single or dual-polarization antenna, rectifier, and power management module. Since the unit is intended for mobile use, the variable available power is monitored, and the duty cycle for wireless data transmission adaptively adjusted through the use of a low-power microcontroller and a custom power management circuit. In sleep mode, the circuit consumes 1 μA at 2.5 V. View full abstract»

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  • A Multiple-Input Boost Converter for Low-Power Energy Harvesting

    Publication Year: 2011 , Page(s): 827 - 831
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (893 KB) |  | HTML iconHTML  

    In this paper, a component efficient multiple-input boost converter is proposed to extract power from multiple low-power energy harvesting sources. The time-multiplexed operation of the proposed converter enables sharing of the power stage between different input sources, leading to a reduced component count. Combined with a novel digital control method and a universal tracking algorithm, maximum power is automatically extracted for all the input sources. A dual-input prototype built with off-the-shelf components validates the overall strategy with commercially available energy transducers. A tracking efficiency of more than 97.5% is demonstrated. View full abstract»

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  • An Inductorless DC–DC Converter for Energy Harvesting With a 1.2-  \mu\hbox {W} Bandgap-Referenced Output Controller

    Publication Year: 2011 , Page(s): 832 - 836
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    We present a fully integrated dc-dc converter for micropower energy harvesting. A 1.2- μW bandgap-referenced output controller provides output regulation at 1.4 V, achieving quiescent power of 3 μW and a maximum overall efficiency of 58% at 11 μW output power. A modified four-phase charge pump provides a 3× voltage boost and a minimum input voltage of 270 mV in free-running mode. Using dual switches driven from both the converter input and output, the chip achieves boost without external excitation or external components. View full abstract»

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  • A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS

    Publication Year: 2011 , Page(s): 837 - 841
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB) |  | HTML iconHTML  

    A 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates redundancy, reassignment, and digital correction to reduce the complexity of analog functions and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator performance is decoupled from matching requirements, so that small and fast dynamic comparators can be used. New analysis discusses the optimum combination of random and deliberate comparator offset to achieve a target effective number of bits (ENOB). This prototype ADC has the highest ENOB and highest sampling frequency of any reported Flash ADC utilizing redundancy. A proof-of-concept prototype achieves no missing codes, 46.6-dB spurious-free dynamic range, and 6.05-bit ENOB at Nyquist input frequency. Fabricated in 90-nm digital CMOS, with a core area of 1.2 mm2, the device consumes 204 mW from a 1.2-V/0.9-V analog/digital supply. View full abstract»

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  • A MM-Wave Configurable VCO Using MCPW-Based Tunable Inductor in 65-nm CMOS

    Publication Year: 2011 , Page(s): 842 - 846
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB) |  | HTML iconHTML  

    This paper describes the modeling and the design of a ladder-structured multilayer-coplanar-waveguide-based tunable differential inductor with wide tuning range and high quality factor. The impacts of process variation on the performance of the inductor and active components are mitigated through postfabrication tuning. A configurable 77-GHz voltage-controlled oscillator (VCO) with a tunable inductor has been designed and implemented in a 65-nm single-poly six-metal bulk CMOS technology. Techniques for tuning the center frequency and increasing the tuning range are described. Under a 1.5-V supply, the measured VCO can be tuned from 67.3 to 77.9 GHz, i.e., 15.8%, while consuming 14.3 mW; the output power is -4.5 dBm, and the phase noise at a 10-MHz offset from the 77-GHz carrier is -108.4 dBc/Hz. This configurable VCO provides a wide tuning range and immunity to process variation. View full abstract»

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  • A 46- \mu\hbox {W} Self-Calibrated Gigahertz VCO for Low-Power Radios

    Publication Year: 2011 , Page(s): 847 - 851
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB) |  | HTML iconHTML  

    This brief presents a 46 μW 0.8-2 GHz tunable oscillator with built-in self-calibrated process, supply voltage, and temperature compensation for applications in low-power radios. With single-point current calibration at room temperature, the proposed voltage-controlled oscillator (VCO) achieves 2.24% frequency accuracy against process variation, 1.6% frequency shift over 0.85- to 1.15-V supply voltage, and 167-ppm/°C temperature sensitivity between -7°C and 76°C. The sub-135-pJ on-chip self-calibration is based on a successive approximation scheme. Our design shows 3.4× improved process variation tolerance, 45× improved supply sensitivity, and 5.2× improved temperature sensitivity, as compared with the free-running VCO without self-calibration. Measurements are taken from 94 chips fabricated in two different lots in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. View full abstract»

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  • Stability Analysis of RF Power Amplifier Envelope Feedback

    Publication Year: 2011 , Page(s): 852 - 856
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    Envelope feedback loop stability criteria are derived based on the Lyapunov stability theorem for time-varying systems using the linear matrix inequality technique. Effects of system parameters on stability are investigated. An envelope feedback system is simulated and measured at RF frequencies, and the derived stability boundaries are in good agreement with simulation and measurement results. View full abstract»

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  • A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets

    Publication Year: 2011 , Page(s): 857 - 861
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    In this brief, we present a dual-mode (high and low) power amplifier (PA) for fourth-generation long-term evolution (LTE) handset applications using a device switching technique to improve the efficiency at low output power. In particular, the effects of the gate voltage variation of the input and output switches on the amplifier performances are described. In addition, a bias control circuit for a dual-mode PA, which can provide the correct voltage to the input and output switches and can be effectively controlled by the mode control voltage, is also proposed. The bias control circuit, the mode switch, and the PA are implemented with the integrated pseudomorphic high-electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) technology on the same chip (i.e., bipolar field effect transistor process). A dual-mode PA with a gain of 27.2 dB, PAE of 34.5%, a ACLRE-UTRA value of -31.2 dBc, and error vector magnitude (EVM) of 2.97% has been achieved in high-power mode; whereas a 22 dB of gain, PAE of 19%, a ACLRE-UTRA value of -31.6 dBc and EVM of 2.84% were measured in the low-power mode with LTE uplink signals. View full abstract»

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  • Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

    Publication Year: 2011 , Page(s): 862 - 866
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    A new multistandard radio receiver architecture is presented to take advantage of nonuniformly controlled analog-to-digital converters (ADCs). By defining the statistical parameter related to the random sampling frequency, a time-quantized random sampling scheme is considered to design a nonuniform sampling-based software defined radio (SDR) multistandard receiver. A relaxed design is proposed for an E-GSM/UMTS/IEEE802.11a multistandard receiver. The designed baseband stage avoids the use of the automatic gain control block, relaxes the nonprogrammable antialiasing filter to the third order, and converts data with a 16-bit ADC at a 124-MHz mean sampling frequency. View full abstract»

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  • A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta–Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation

    Publication Year: 2011 , Page(s): 867 - 871
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply. View full abstract»

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  • Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit \Delta \Sigma ADCs

    Publication Year: 2011 , Page(s): 872 - 876
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    This paper presents a new vector-based mismatch-shaping technique for multibit ΔΣ analog-to-digital converters. It has low hardware complexity, which only linearly grows with the number of unit digital-to-analog converter elements. Compared with the existing low-complexity vector-based technique, this technique does not require extra filters and has much better mismatch-shaping effect and stability. Simulations under various conditions prove its validity. View full abstract»

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  • A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling

    Publication Year: 2011 , Page(s): 877 - 881
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    This brief presents a Volterra series model to evaluate the impact of substrate noise on Flash analog-to-digital converters. The proposed approach first relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. The analysis then expresses the resulting sampling distortion power by also considering the comparator's nonlinearities and thus models the signal-to-noise-and-distortion ratio (SNDR) of the converter. In particular, it is shown that substrate noise causes an FM modulation of the clock, and the resulting timing error is a joint effect of AM-FM modulation of the input signal and the coupled noise. The derivation of the analytical expression is also valid for any multitone ground perturbation and is validated on a high-resolution Flash converter. The developed nonlinear model for the SNDR is found to almost double the noise amplitude range compared with the linear model, thus predicting the impact of realistically large noise signals. View full abstract»

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  • Systematic Analysis of Interleaved Digital-to-Analog Converters

    Publication Year: 2011 , Page(s): 882 - 886
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (510 KB) |  | HTML iconHTML  

    A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined. View full abstract»

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  • A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers

    Publication Year: 2011 , Page(s): 887 - 891
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (926 KB) |  | HTML iconHTML  

    An area-efficient 9-bit digital-to-analog converter (DAC) for application in current-mode active-matrix organic light-emitting diode mobile display drivers is presented. To reduce the chip size, the proposed DAC is realized with a novel switched-current architecture, which periodically receives digital bits one by one in series to perform single bit conversion. A high-performance current-mode S/H circuit is also suggested in order to increase the sampling speed and linearity of the DAC. The prototype 9-bit DAC occupies only 0.014 mm2 per channel in a 0.35- μm CMOS process and achieves a 100-kS/s conversion rate at a static current of 10 μA under a 3.3-V supply. The measured maximum integral and differential nonlinearities are 1.6 and 0.8 LSB, respectively. Measured maximum interchannel current output deviations in the best and the worst chips are 15 and 35 nA, respectively. View full abstract»

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  • Dynamic Load Modulation With a Reconfigurable Matching Network for Efficiency Improvement Under Antenna Mismatch

    Publication Year: 2011 , Page(s): 892 - 896
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    This brief presents the application of a reconfigurable matching network (RMN) to improve the efficiency of an RF power amplifier (PA) using dynamic load modulation techniques under different antenna mismatch conditions. By changing the RMN state, a near-optimal output impedance is presented to the PA, achieving high efficiency for all input-driven levels. Simulations show efficiency enhancement, while nonlinear distortion can be mitigated using digital predistortion. It will be also shown that under severe mismatch conditions, using an RMN, significant efficiency and linearity improvements can be achieved. View full abstract»

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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope