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IEEE Computer Architecture Letters

Issue 2 • Date July-Dec. 2011

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Displaying Results 1 - 11 of 11
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • Publication information

    Publication Year: 2011, Page(s): c2
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  • Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity

    Publication Year: 2011, Page(s):29 - 32
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (145 KB) | HTML iconHTML

    The class of modern datacenters recently coined as “warehouse scale computers” (WSCs) has traditionally been embraced as homogeneous computing platforms. However, due to frequent machine replacements and upgrades, modern WSCs are in fact composed of diverse commodity microarchitectures and machine configurations. Yet, current WSCs are designed with an assumption of homogeneity, leavi... View full abstract»

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  • Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks

    Publication Year: 2011, Page(s):33 - 36
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB) | HTML iconHTML

    This paper introduces packet chaining, a simple and effective method to increase allocator matching efficiency and hence network performance, particularly suited to networks with short packets and short cycle times. Packet chaining operates by chaining packets destined to the same output together, to reuse the switch connection of a departing packet. This allows an allocator to build up an efficie... View full abstract»

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  • Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities

    Publication Year: 2011, Page(s):37 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (142 KB) | HTML iconHTML

    As technology scales, device reliability is becoming a fundamental problem. Even though manufacture test can guarantee product quality, due to various types of wearout and failure modes, permanent faults appear in the filed is becoming an increasingly important and real problem. Such types of wear-out creates permanent faults in devices during their lifetime, but after release to the user. In this... View full abstract»

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  • Fault-Tolerant Vertical Link Design for Effective 3D Stacking

    Publication Year: 2011, Page(s):41 - 44
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes the bottleneck, thus demanding larger memory amounts inside the chip. The most accepted solution to implement vertical links between stacked dies is by using Through Silicon Vias (T... View full abstract»

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  • Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor

    Publication Year: 2011, Page(s):45 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    This paper describes our experience with profiling and optimizing physical locality for the distributed shared cache (DSC) in Tilera's Tile multicore processor. Our approach uses the Tile Processor's hardware performance measurement counters (PMCs) to acquire page-level access pattern profiles. A key problem we address is imprecise PMC interrupts. Our profiling tools use binary analysis to correct... View full abstract»

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  • Multilevel Cache Modeling for Chip-Multiprocessor Systems

    Publication Year: 2011, Page(s):49 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    This paper presents a simple analytical model for predicting on-chip cache hierarchy effectiveness in chip multiprocessors (CMP) for a state-of-the-art architecture. Given the complexity of this type of systems, we use rough approximations, such as the empirical observation that the re-reference timing pattern follows a power law and the assumption of a simplistic delay model for the cache, in ord... View full abstract»

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  • On Supporting Rapid Thermal Analysis

    Publication Year: 2011, Page(s):53 - 56
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    Detailed thermal analysis is usually performed exclusively at design time since it is a computationally intensive task. In this paper, we introduce a novel methodology for fast, yet accurate, thermal analysis. The introduced methodology is software supported by a new open source tool that enables hierarchical thermal analysis with adaptive levels of granularity. Experimental results prove the effi... View full abstract»

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  • Cover 3

    Publication Year: 2011, Page(s): c3
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  • IEEE Computer Society [society information]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

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Meet Our Editors

Editor-in-Chief
José Martinez
Cornell University
336 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
e-mail: martinez@cornell.edu