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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 12 • Date Dec. 2011

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • Outgoing Editorial

    Publication Year: 2011 , Page(s): 2805 - 2807
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  • Sinusoidal Clock Sampling for Multigigahertz ADCs

    Publication Year: 2011 , Page(s): 2808 - 2815
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    Current multigigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock to improve SFDR. Whereas a square-wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but a lower jitter spectrum. To verify this concept, an 8 GS/s, 4b flash ADC with a sinusoidal clock is designed and experimentally measured, achieving a figure-of-merit of 0.86 pJ/conv-step based upon effective resolution bandwidth (ERBW), and 0.2 pJ/conv-step based upon sampling rate. View full abstract»

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  • Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

    Publication Year: 2011 , Page(s): 2816 - 2828
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1271 KB) |  | HTML iconHTML  

    A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@1.2 V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach. View full abstract»

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  • A Rigorous Approach to the Robust Design of Continuous-Time \Sigma \Delta Modulators

    Publication Year: 2011 , Page(s): 2829 - 2837
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (941 KB) |  | HTML iconHTML  

    In this paper we present a framework for robust design of continuous-time ΣΔ modulators. The approach allows to find a modulator which maintains its performance (stability, guar anteed peak SNR, . . .) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time ΣΔ modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework. View full abstract»

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  • Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs

    Publication Year: 2011 , Page(s): 2838 - 2848
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1129 KB) |  | HTML iconHTML  

    This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme. The test time of these designs is dominated by the long calibration time required prior to conducting the final testing. To reduce overall test time, we present a two-step calibration approach that significantly reduces calibration time without compromising test coverage. In addition, by analyzing the data obtained in calibration, devices that fail certain static or dynamic specifications can be identified without incurring any additional test time beyond calibration, thereby enabling early rejection. To minimize calibration time and maximize failing symptoms for fault detection, we propose using specific calibration stimuli. Simulation results for a pipelined ADC shows that the proposed strategy reduces the total test time by 80%. This is achieved by reducing the calibration time, as well as by prescreening a good fraction of defective devices that fail static and dynamic specifications including the gain/offset errors and the effective number of bits (ENOB). View full abstract»

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  • A Low Power Content Addressable Memory Using Low Swing Search Lines

    Publication Year: 2011 , Page(s): 2849 - 2858
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1613 KB) |  | HTML iconHTML  

    This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with VDD = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm2. Its maximum operating frequency is 210 MHz. View full abstract»

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  • Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

    Publication Year: 2011 , Page(s): 2859 - 2871
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB) |  | HTML iconHTML  

    Reliability and variability have become big design challenges facing submicrometer SRAM designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Postlayout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65 nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on the SRAM array. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB reduces the read failure probability from 0.32% to 0.05% and the SNM degradation from 10.9% to 2.6% at 10 years aging time. In addition, the proposed ABB enhances the soft errors immunity of the SRAM cell by reducing the critical charge degradation from 12.7% to 3.4% at 10 years aging time. View full abstract»

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  • Estimation of Magnitude of Self-Induced Oscillations via Piecewise Quadratic Lyapunov Functions

    Publication Year: 2011 , Page(s): 2872 - 2881
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1165 KB) |  | HTML iconHTML  

    A Lyapunov approach is developed in this paper for estimation of the magnitude of self-induced oscillations for systems with piecewise linear elements. The oscillatory trajectories are bounded by invariant level sets of a piecewise quadratic Lyapunov function. An optimization problem with bilinear-matrix-inequality constraints is formulated to minimize the invariant level set and to obtain tight bound for oscillatory trajectories. Several examples demonstrate the effectiveness of the new method on analysis of self-induced oscillations. View full abstract»

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  • Pinning Complex Delayed Dynamical Networks by a Single Impulsive Controller

    Publication Year: 2011 , Page(s): 2882 - 2893
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3428 KB) |  | HTML iconHTML  

    In this paper, we propose a novel approach for analyzing synchronization stability in a complex delayed dynamical network via impulsive control. We present the sufficiency conditions for pinning synchronization stability of single impulsive controller for an undirected complex delayed dynamical network in the presence of identical coupling delays between nodes. We also show that a single impulsive controller can always pin a given complex delayed dynamical network to a homogenous solution, provided that both the coupling strength and coupling delay are properly selected. Subsequently, the results are illustrated by a typical scale-free (SF) network composing of the representative oscillators and a small-world (SW) neuronal network. Numerical simulations with three kinds of the homogenous solutions, including an equilibrium point, a periodic orbit, and a chaotic orbit, are finally given to demonstrate the effectiveness of the proposed control methodology. View full abstract»

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  • An Analytical Algorithm for Pi-Network Impedance Tuners

    Publication Year: 2011 , Page(s): 2894 - 2905
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1077 KB) |  | HTML iconHTML  

    In this paper, an analytical tuning algorithm for a pi-network impedance tuner is presented. The pi-network consists of tunable capacitors with finite tuning range, and a fixed value inductor. The algorithm is able to determine all tunable network component values for matching any given load impedance. The resulting matching performance measured either in terms of the input VSWR or transducer gain, is equivalent to that obtained from a commercial iterative optimization methods, but the algorithm runs significantly faster than the optimizer simulation. The proposed algorithm can be extended to a network tuner topology comprised of four or less tunable components as long as it can be transformed into an equivalent pi-network topology. It is suitable for the design of fixed as well as tunable matching networks. View full abstract»

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  • DRAM Yield Analysis and Optimization by a Statistical Design Approach

    Publication Year: 2011 , Page(s): 2906 - 2918
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1971 KB) |  | HTML iconHTML  

    In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits. View full abstract»

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  • High Performance Control Design for Dynamic Voltage Scaling Devices

    Publication Year: 2011 , Page(s): 2919 - 2930
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1276 KB) |  | HTML iconHTML  

    Dynamic voltage scaling (DVS) is an important method in managing dynamically the system supply voltage for efficient power reduction. This approach is applied in very large scale integration (VLSI). A dc-dc converter is an electronic device which allows to vary the voltage and, thus, to implement DVS technique. In this paper, a high-performance controller is presented for a novel discrete DVS converter. This controller is developed with the aim to deal with the unknown resistive component of the load as well as to minimize the dissipated energy and current peaks, what is very important in the field of microelectronics. Current peaks and power consumption are minimized by computing an optimal evolution for the voltage reference. Likewise, an adaptive controller is proposed to deal with the unknown load resistive parameter. Consequently, the obtained advanced controller can acquires a high consideration on electronic devices. View full abstract»

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  • Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes

    Publication Year: 2011 , Page(s): 2931 - 2943
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (957 KB) |  | HTML iconHTML  

    Emerging applications such as flash-based storage systems and 10 gigabit Ethernet require that there is no error floor even at bit error rates as low as 10-12 or so. It has been found that trapping sets are responsible for the error floors of many LDPC codes with AWGN channels. This paper presents a hardware based backtracking scheme to break the trapping sets at runtime for lowering the error floor of quasi-cyclic LDPC codes. Backtracking is implemented as a self-contained module that can be interfaced to any generic reconfigurable iterative decoder for QC-LDPC codes. The backtracking module and a reconfigurable decoder are implemented with a FPGA and an 180 nm standard cell library. The results indicate that the overhead of backtracking is modest - about 5% in terms of logic and 13% in terms of memory for the first level backtracking and 14% in terms of logic and 46% in terms of memory for a two-level backtracking scheme. Furthermore, it is shown that the increase in latency due to backtracking is modest in the average case and can be controlled by the system designer by choosing the appropriate values for the number of trials and the number of iterations of the backtracking module. View full abstract»

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  • A Reachability-Based Method for Large-Signal Behavior Verification of DC-DC Converters

    Publication Year: 2011 , Page(s): 2944 - 2955
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (974 KB) |  | HTML iconHTML  

    A method for large-signal behavior verification of power electronics dc-dc converters subject to uncertain variations in operating conditions is proposed. This method relies on the computation of the reach set, i.e., the set of all possible trajectories that arise from different initial conditions, unknown-but-bounded inputs, and inherent switching. Large-signal behavior verification is accomplished by checking that the reach set remains within the region of state space defined by performance requirements, e.g., output voltage tolerance specifications, component voltage and current limits. Algorithms to solve the reachability problem for power electronics converters operating under both open- and closed-loop control are provided along with simulations illustrating the proposed method. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2011 , Page(s): 2956
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  • 2011 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 58

    Publication Year: 2011 , Page(s): 2957 - 2990
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2011 , Page(s): C3
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras