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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec. 2011

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2011, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2011, Page(s): C2
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  • Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery

    Publication Year: 2011, Page(s):1773 - 1785
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (846 KB) | HTML iconHTML

    State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse o... View full abstract»

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  • A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips

    Publication Year: 2011, Page(s):1786 - 1799
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1111 KB) | HTML iconHTML

    Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages, such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to... View full abstract»

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  • Field Programmable Stateful Logic Array

    Publication Year: 2011, Page(s):1800 - 1813
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1421 KB) | HTML iconHTML

    Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, i... View full abstract»

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  • Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits

    Publication Year: 2011, Page(s):1814 - 1827
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (931 KB)

    In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of... View full abstract»

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  • SparseRC: Sparsity Preserving Model Reduction for RC Circuits With Many Terminals

    Publication Year: 2011, Page(s):1828 - 1841
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB) | HTML iconHTML

    A novel model order reduction (MOR) method, SparseRC, for multiterminal RC circuits is proposed. Specifically tailored to systems with many terminals, SparseRC employs graph-partitioning and fill-in reducing orderings to improve sparsity during model reduction, while maintaining accuracy via moment matching. The reduced models are easily converted to their circuit representation. These contain muc... View full abstract»

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  • An Algorithmic Study of Exact Route Matching for Integrated Circuits

    Publication Year: 2011, Page(s):1842 - 1855
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (635 KB) | HTML iconHTML

    As system-on-chip designs are getting more popular, the importance of design automation for analog and mixed-signal integrated circuits is increasing. In this paper, we study the problem of exact route matching, which is an important physical design constraint commonly imposed on specific analog signals for the purpose of correct functionality. For this, we first propose a mathematical formulation... View full abstract»

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  • Pulsed-Latch Aware Placement for Timing-Integrity Optimization

    Publication Year: 2011, Page(s):1856 - 1869
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (795 KB) | HTML iconHTML

    Utilizing pulsed-latches in circuit designs is one emerging solution to timing improvements. Pulsed-latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If the pulse generator and pulsed-latches are not placed properly, however, pulse-width degradations at pulsed-latches and thus timing violations might occur. In this paper, w... View full abstract»

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  • Post-Placement Power Optimization With Multi-Bit Flip-Flops

    Publication Year: 2011, Page(s):1870 - 1882
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1123 KB) | HTML iconHTML

    Optimization for power is always one of the most important design objectives in modern nanometer integrated circuit design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. This paper presents: 1) a novel design methodology of applying multi-bit flip-flops at the post-placement stage, which can be seamlessly integrated... View full abstract»

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  • Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures

    Publication Year: 2011, Page(s):1883 - 1896
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (874 KB) | HTML iconHTML

    3-D stacked systems reduce communication delay in multiprocessor system-on-chips (MPSoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates temperature-induced problems such as reliability degradation. Liquid cooling is a highly efficient solution to overcome the accelerated thermal problems in 3-D architectures; h... View full abstract»

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  • CNoC: High-Radix Clos Network-on-Chip

    Publication Year: 2011, Page(s):1897 - 1910
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB) | HTML iconHTML

    Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose: 1) a high-radix router architecture with virtual output queue... View full abstract»

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  • Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out

    Publication Year: 2011, Page(s):1911 - 1922
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB) | HTML iconHTML

    The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring li... View full abstract»

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  • Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

    Publication Year: 2011, Page(s):1923 - 1934
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1013 KB) | HTML iconHTML

    As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) dur... View full abstract»

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  • 2011 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 30

    Publication Year: 2011, Page(s):1935 - 1956
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2011, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2011, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu