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Design & Test of Computers, IEEE

Issue 4 • Date July-Aug. 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Front cover]

    Publication Year: 2011, Page(s): c2
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  • Call for Papers

    Publication Year: 2011, Page(s): 1
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  • Contents

    Publication Year: 2011, Page(s):2 - 3
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  • Toward FPGA-Enabled Scientific Computing

    Publication Year: 2011, Page(s): 4
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  • Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research

    Publication Year: 2011, Page(s):6 - 7
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  • Numerical Data Representations for FPGA-Based Scientific Computing

    Publication Year: 2011, Page(s):8 - 17
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    Data representation is an important problem for scientific computing problems that are mapped to FPGAs. The key challenge here is to derive best trade-offs between precision and performance. This article describes methods to manage the complexity associated with the analysis of data representation techniques so that we thereby understand precision/performance trade-offs. View full abstract»

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  • Designing Custom Arithmetic Data Paths with FloPoCo

    Publication Year: 2011, Page(s):18 - 27
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB) | HTML iconHTML

    Efficient implementation of basic, data-path circuit elements is of fundamental importance to achieving high performance in FPGA-based acceleration of scientific computing. This work presents a leading effort to automate the production of pipelined data-path circuits for implementing numerical functions. View full abstract»

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  • High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations

    Publication Year: 2011, Page(s):28 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    Computational fluid dynamics is a classical problem in high-performance computing. In order to make use of an existing code base in this field, the use of high-level design tools is an imperative. The authors explore the use of the Impulse C design tools for a Navier-Stokes implementation. View full abstract»

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  • Data Reorganization and Prefetching of Pointer-Based Data Structures

    Publication Year: 2011, Page(s):38 - 47
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    The significant acceleration of code containing pointer-based data structures is beyond the reach of most high-level synthesis tools, yet a large amount of legacy scientific computing code contains these structures. This article presents a method to cope with such code within a reconfigurable computing context. View full abstract»

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  • FPGA-Based Particle Recognition in the HADES Experiment

    Publication Year: 2011, Page(s):48 - 57
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (517 KB) | HTML iconHTML

    In recent years, FPGAs have been on the front line of several experimental, fundamental physics programs. This article discusses the use of FPGAs in particle recognition for filtering the huge quantity of data generated by such experiments. View full abstract»

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  • Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture

    Publication Year: 2011, Page(s):58 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1233 KB) | HTML iconHTML

    The significant growth in the quantity of data in biology and related fields has spawned the need for novel computational solutions. The authors show how a key search task in proteomics, the large-scale study of proteins, can be accelerated by several orders of magnitude by the use of FPGA-based hardware. View full abstract»

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  • An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing

    Publication Year: 2011, Page(s):68 - 77
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB) | HTML iconHTML

    As part of their ongoing work with the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC), the authors are developing a complete tool chain for FPGA-based acceleration of scientific computing, from early-stage assessment of applications down to rapid routing. This article provides an overview of this tool chain. View full abstract»

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  • Cyberphysical Systems: Workload Modeling and Design Optimization

    Publication Year: 2011, Page(s):78 - 87
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (567 KB) | HTML iconHTML

    Built to interact with the physical world, a cyberphysical system (CPS) must be efficient, reliable, and safe. To optimize such systems, a science of CPS design considering workload characteristics (e.g., self-similarity and nonstationarity) must be established. CPS modeling and design are greatly improved when statistical physics approaches - such as master equations, renormalization group theory... View full abstract»

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  • Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores

    Publication Year: 2011, Page(s):88 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (633 KB) | HTML iconHTML

    This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33&#... View full abstract»

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  • Getting Your Bits in Order

    Publication Year: 2011, Page(s):98 - 101
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  • Panel Summaries

    Publication Year: 2011, Page(s):102 - 105
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  • CEDA Currents

    Publication Year: 2011, Page(s):106 - 107
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  • Test Technology TC Newsletter

    Publication Year: 2011, Page(s):108 - 109
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2011, Page(s):110 - 111
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  • FPGAs, Programming Models, and Kit Cars

    Publication Year: 2011, Page(s): 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB) | HTML iconHTML

    The degree of parallelism and ability to customize the RAM and data path architecture to the computation have enabled FPGAs to replace custom ASIC chips in many designs. Teams of highly skilled engineers crafting HDL code are the Formula-1 teams of the FPGA world, optimizing data paths from the thousands of programmable elements in an FPGA. View full abstract»

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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty