# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2011, Page(s):C1 - C4
Cited by:  Papers (1)
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2011, Page(s): C2
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• ### CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs

Publication Year: 2011, Page(s):2141 - 2148
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Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. This needs substantial overheads in both area and power. Existing logic families that minimize switching-noise generation, such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a ne... View full abstract»

• ### Efficient Modulo $2^{n}+1$ Multipliers

Publication Year: 2011, Page(s):2149 - 2157
Cited by:  Papers (10)
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Area-time efficient modulo (2n+1) multipliers are proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished-1. By using the radix-4 Booth recoding, the new multipliers reduce the number of the partial products to n/2 for n even and (n+1)/2 for n odd except for one correction term. Alth... View full abstract»

• ### Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

Publication Year: 2011, Page(s):2158 - 2169
Cited by:  Papers (18)
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A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect tr... View full abstract»

• ### A Novel Test Flow for One-Time-Programming Applications of NROM Technology

Publication Year: 2011, Page(s):2170 - 2183
Cited by:  Papers (4)
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The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for... View full abstract»

• ### A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories

Publication Year: 2011, Page(s):2184 - 2194
Cited by:  Papers (4)
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With the advent of deep-submicrometer VLSI technology, the capacity and performance of semiconductor memory chips is increasing drastically. This advantage also makes it harder to maintain good yield. Diagnostics and redundancy repair methodologies thus are getting more and more important for memories, including embedded ones that are popular in system chips. In this paper, we propose an efficient... View full abstract»

• ### Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

Publication Year: 2011, Page(s):2195 - 2208
Cited by:  Papers (6)
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As process technology scales, the design effort and nonrecurring engineering (NRE) costs associated with the development of integrated circuits is becoming extremely high. Structured ASICs offer one solution to these problems. However, to realize their full potential, their performance and cost advantages, architectures, and CAD must be fully understood. We believe that this can lead to wider adop... View full abstract»

• ### Gate Leakage Impact on Full Open Defects in Interconnect Lines

Publication Year: 2011, Page(s):2209 - 2220
Cited by:  Papers (5)
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An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxid... View full abstract»

• ### A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption

Publication Year: 2011, Page(s):2221 - 2228
Cited by:  Papers (16)
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This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in ... View full abstract»

• ### An Analytical Model Relating FPGA Architecture to Logic Density and Depth

Publication Year: 2011, Page(s):2229 - 2242
Cited by:  Papers (10)
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This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup-table and cluster, the number of used inputs per cluster, and the depth of the circuit after... View full abstract»

• ### Power Delivery for Multicore Systems

Publication Year: 2011, Page(s):2243 - 2255
Cited by:  Papers (3)
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As the industry moves from single- to multicore processors, the challenges of how to reliably design and analyze power delivery for such systems arise. We study various workload assignments to cores and their effect on the global power supply noise and ground bounce. We provide a detailed analysis of single and multiple cores and develop analytical formulas to capture the power supply noise and gr... View full abstract»

• ### Clock Distribution Networks in 3-D Integrated Systems

Publication Year: 2011, Page(s):2256 - 2266
Cited by:  Papers (17)  |  Patents (1)
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3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test cir... View full abstract»

• ### 0.84 ps Resolution Clock Skew Measurement via Subsampling

Publication Year: 2011, Page(s):2267 - 2275
Cited by:  Papers (8)  |  Patents (3)
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An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogra... View full abstract»

• ### Full-Spectrum Spatial–Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits

Publication Year: 2011, Page(s):2276 - 2289
Cited by:  Papers (3)
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This paper presents NanoHeat, a multi-resolution full-chip dynamic integrated circuit (IC) thermal analysis solution, that is accurate down to the scale of individual gates and transistors. NanoHeat unifies nanoscale and macroscale dynamic thermal physics models, for accurate characterization of heat transport from the gate and transistor level up to the chip-package level. A non-homogeneous Arnol... View full abstract»

• ### A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling

Publication Year: 2011, Page(s):2290 - 2302
Cited by:  Papers (25)  |  Patents (1)
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This paper presents a generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC). The proposed addressing scheme considers the continuous-flow operation with minimum shared memory requirements. To improve throughput, parallel high-radix process... View full abstract»

• ### MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Publication Year: 2011, Page(s):2303 - 2316
Cited by:  Papers (6)
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Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This paper pres... View full abstract»

• ### Fast Bit-Parallel Shifted Polynomial Basis Multiplier Using Weakly Dual Basis Over $GF(2^{m})$

Publication Year: 2011, Page(s):2317 - 2321
Cited by:  Papers (4)
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In this paper, we present a new method to compute the Mastrovito matrix for GF(2m) generated by an arbitrary irreducible polynomial using weakly dual basis of shifted polynomial basis. In particular, we derive the explicit formulas of the proposed multiplier for special type of irreducible pentanomial xm+xk3+xk2+xk... View full abstract»

• ### Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors

Publication Year: 2011, Page(s):2322 - 2325
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We propose a low cost scheme for the dynamic compensation in the field of undesired skew and duty cycle variations of local clocks of high performance microprocessors and high end ASICs. Compared to alternate approaches, our solution features lower power consumption, smaller compensation error, and a lower or comparable area overhead. View full abstract»

• ### Low Cost Hardware Implementation of Logarithm Approximation

Publication Year: 2011, Page(s):2326 - 2330
Cited by:  Papers (20)
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A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results ar... View full abstract»

• ### Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets

Publication Year: 2011, Page(s):2330 - 2335
Cited by:  Papers (9)
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Defect screening is a major challenge for nanoscale CMOS circuits, especially since many defects cannot be accurately modeled using known fault models. The effectiveness of test methods for such circuits can therefore be measured in terms of the coverage obtained for unmodeled faults. In this paper, we present a new defect-oriented dynamic LFSR reseeding technique for test-data compression. The pr... View full abstract»

• ### A Routing-Aware ILS Design Technique

Publication Year: 2011, Page(s):2335 - 2338
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The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be plac... View full abstract»

• ### High Productivity Circuit Methodology for a Semi-Custom Embedded Processor

Publication Year: 2011, Page(s):2339 - 2342
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A high productivity methodology for implementing custom circuit blocks inside a synthesized microprocessor is presented. A cell-based design style and script-based preroutes are used with a commercial place and route tool, enabling fast layout for custom blocks. The design methodology supports domino logic, register files, and random logic designs. A semi-custom MIPS microprocessor targeted for th... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2011, Page(s): 2343
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Publication Year: 2011, Page(s): 2344
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu