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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 11 • Date Nov. 2011

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  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • A Comparative Analysis of Peaking Methods for Output Stages of Broadband Amplifiers

    Publication Year: 2011 , Page(s): 2581 - 2589
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB) |  | HTML iconHTML  

    This paper presents a general analysis of peaking methods in output stages of amplifiers for broadband communication systems. It is shown that common peaking methods, although providing significant signal bandwidth enhancement ratios (BWER), are limited to 30%-50% of their speed potential by output matching requirements. A modified T-coil peaking is analyzed which enhances both signal bandwidth and output matching frequency range by up to 200% compared to common peaking methods. A broadband amplifier using this inductive output matching with 69-GHz bandwidth implemented in a 0.25 μm SiGe BiCMOS technology is presented to prove the validity of the analysis. View full abstract»

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  • An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation

    Publication Year: 2011 , Page(s): 2590 - 2603
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1571 KB) |  | HTML iconHTML  

    We propose a time-domain technique that significantly improves resolution of an RF-DAC. As an alternative to resorting to various resolution improvement attempts in the amplitude domain or through quantization noise shaping, pulsewidth modulation (PWM) of a single unit switching device is employed with fine timing accuracy easily afforded by advanced CMOS technology. The PWM is categorized into centered PWM and noncentered PWM depending on the relative pulse position, and their performance and implementation methods are compared. The technique is examined in the context of a commercial EDGE polar transmitter realized in 65 nm CMOS, which employs an amplitude modulator with basic 10-bit amplitude resolution limited by the RF-DAC switching device mismatches. The proposed architectures with centered PWM and noncentered PWM achieve the worst case resolution improvement of 2.2 bits and 2.5 bits, respectively, assuming 20-ps worst case time granularity of the PWM signal controls. View full abstract»

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  • A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass \Delta \Sigma Modulators

    Publication Year: 2011 , Page(s): 2604 - 2613
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1872 KB) |  | HTML iconHTML  

    High-pass (HP) delta-sigma (ΔΣ) modulators possess the qualities of high immunity to low-frequency noise and direct digitisation at intermediate frequency (IF) stage,. This paper presents three loop-filter alternatives for second-order HP ΔΣ modulator and performs a comparative analysis. The two of the three architectures have already been utilized for low-pass (LP) modulators while the third one has not been explored before. This particular topology mitigates the shortcomings of the other two modulator architectures. It is a mixture of feedforward and feedback structures and hence takes advantages of both of them. The topology is less sensitive to the nonlinearities of the operational transconductance amplifiers (OTAs) and hence has low distortion. The output swing requirements of the OTA are minimized as they just process the quantization noise. This way the design of the OTA is fairly relaxed with reduced power consumption. The analog adder before the quantizer is also simplified as there are just two branches to add in contrast to three branches for pure feedforward topologies. This makes the modulator more robust against comparator offset, hysteresis and metastability. Hence this adder can be implemented passively without increasing the design requirements on comparator enormously. View full abstract»

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  • Multiple Event Time-to-Digital Conversion-Based Pulse Digitization for a 250 MHz Pulse Radio Ranging Application

    Publication Year: 2011 , Page(s): 2614 - 2622
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (639 KB) |  | HTML iconHTML  

    A pulse digitizing approach for time-of-arrival pulse radio based ranging is introduced. It is based on a bank of time-to-digital converter (TDC) cores. A comparator bank triggers these multiple TDCs. This multiple event approach has advantages over classic single TDC solutions when facing unknown channel gains, noise corruption, and strong fading channel behavior. Pulses are digitized in a way that is superior in terms of performance versus power to classic A/D conversion. A power effort figure ξ and a new SNDR metric are introduced, easing performance comparison of pulse digitizers. A low power 8 channel digitizing system with a resolution of δtring=62.5 ps is presented for a cm accurate ranging application. The asynchronous, event-based nature of the architecture requires nonstrobed comparators to fire value crossing events. A dynamic range of 800:1 is realized. The digitization device is designed for 130 nm standard CMOS. An analog-baseband front-end I-Q energy detection and comparator threshold level configuration D/As are added to the design. The complete system is designed to consume 4 mW. View full abstract»

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  • A CMOS Colpitts VCO Using Negative-Conductance Boosted Technology

    Publication Year: 2011 , Page(s): 2623 - 2635
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (762 KB) |  | HTML iconHTML  

    A circuit topology suitable for a low-voltage low-power Colpitts voltage-controlled oscillator (VCO) is presented in this paper. By employing inductors for a negative-conductance boosted structure, the dc power consumption of the Colpitts VCO can be effectively reduced. Based on the proposed architecture, the VCO fabricated in 0.18-μm CMOS exhibits a measured 1.3% tuning range around 30 GHz. Operating at a supply voltage of 1.0 V, the VCO core consumes 2.3-mW dc power, and the measured phase noise is -104.1 dBc/Hz at 1-MHz offset. Compared to the recently published 20 to 30-GHz 0.18-μm CMOS VCOs, this work achieves a reduced supply voltage, minimized dc power consumption, small chip size, superior figure-of-merit (FOM), and better figure-of-merit including the tuning range (FOMT). Formulas for considering the nonlinear characteristics of varactors and active devices are also presented, and the accuracy of predicting the VCO tuning curve is validated by measurement. View full abstract»

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  • A CMOS Highly Linear Digitally Programmable Active-RC Design Approach

    Publication Year: 2011 , Page(s): 2636 - 2646
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1033 KB) |  | HTML iconHTML  

    A new approach providing the active-RC integrator with programmable time constant is proposed. An inherently linear current division network (CDN) preserving the high linearity property of the active RC technique while providing wide tuning characteristics is adopted. The proposed integrator provides wider tuning range, and higher tuning resolution accompanied with better linearity and/or reduced area than what could be obtained from capacitor and resistor banks. The proposed integrator uses two opamps per integrator just like its MOSFET-C counterpart but it inherently exhibits better linearity and wider tuning range particularly for low voltage supply. A reconfigurable filter exhibiting complex bandpass and normal lowpass responses is realized. Experimental results obtained from a 4th-order filter fabricated in a standard 0.18 μm CMOS process are given. The complex and lowpass filters achieve in-band spurious-free dynamic ranges (SFDRs) of about 70 dB and 71 dB for bandwidths of 1 MHz and 5.5 MHz, respectively. View full abstract»

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  • An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links

    Publication Year: 2011 , Page(s): 2647 - 2660
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2019 KB) |  | HTML iconHTML  

    This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no “comma” characters need to be transmitted during these pauses. As soon as a new event needs to be transmitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 μm CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second). View full abstract»

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  • An Integrated Low-Noise Sensing Circuit With Efficient Bias Stabilization for CMOS MEMS Capacitive Accelerometers

    Publication Year: 2011 , Page(s): 2661 - 2672
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1556 KB) |  | HTML iconHTML  

    A sensing circuit in 0.35 μm CMOS technology for CMOS MEMS capacitive accelerometers has been designed in this work with emphasis on managing noise, sensor offset, and the dc bias at input terminals. The issue of dc bias is particularly addressed and an efficient method is proposed. An example of integrating surface micromachined sensors and the designed sensing circuits on the same chip is demonstrated. Experimental results showed that the proposed circuit led to good noise performance, the random offset in the sensors was efficiently compensated, and the input dc bias voltage was well maintained. The sensitivity of the accelerometer is 457 mV/g. The output noise floor is 54 μg/√Hz, which corresponds to an effective capacitance noise floor of 0.0162 aF/√Hz. The total area of the dual-axis surface micromachined accelerometer chip is 5.66 mm2 and the current consumption is 1.56 mA under a 3.3 V voltage supply. View full abstract»

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  • An Optically Programmable SoC for an Autonomous Mobile mm ^{3} -Sized Microrobot

    Publication Year: 2011 , Page(s): 2673 - 2685
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2618 KB) |  | HTML iconHTML  

    Recent progresses in miniaturization of sensors and actuators have yielded to the first attempt to create an mm3 -sized autonomous robot with sensing capabilities called I-SWARM. The robot is conceived to interact with other I-SWARM robots in order to create a robotic swarm. It is provided with a locomotion unit, an infrared communication system, a contact sensor, solar cells for powering, and a system on chip (SoC) that acts as the brain of the robot. All these components are mounted over a flexible printed circuit board, being I-SWARM a real system in package (SiP). The SoC communicates with other I-SWARMs, sense its environment, processes data and takes decisions, as for example moving, with less than 1.5 mW. Different electronic circuits (power electronics, buffers, ADCs, DACs, control units, analog transducers, and even an oscillator) have been embedded in the SoC due to the limited area, less than 3 × 3 mm2. The SoC is reprogrammable optically in order to change the behavior of the microrobot. View full abstract»

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  • Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set {2^{n} - 1, 2^{n}, 2^{n} + 1}

    Publication Year: 2011 , Page(s): 2686 - 2697
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo operation. In this paper, a simple and fast scaling algorithm for the three-moduli set {2n - 1, 2n, 2n + 1} RNS is proposed. The complexity of intermodulo operation has been resolved by a new formulation of scaling an integer in RNS domain by one of its moduli. By elegant exploitation of the Chinese Remainder Theorem and the number theoretic properties for this moduli set, the design can be readily implemented by a standard cell based design methodology. The low cost VLSI architecture without any read-only memory (ROM) makes it easier to fuse into and pipeline with other residue arithmetic operations of a RNS-based processor to increase the throughput rate. The proposed RNS scaler possesses zero scaling error and has a critical path delay of only 2[log2n]+ 9 units in unit-gate model. Besides the scaled residue numbers, the scaled integer in normal binary representation is also produced as a byproduct of this process, which saves the residue-to-binary converter when the binary representation of scaled integer is also required. Our experimental results show that the proposed RNS scaler is smaller and faster than the most area-efficient adder-based design and the fastest ROM-based design besides being the most power efficient among all scalers evaluated for the same three-moduli set. View full abstract»

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  • Tapered-Vth Approach for Energy-Efficient CMOS Buffers

    Publication Year: 2011 , Page(s): 2698 - 2707
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (979 KB) |  | HTML iconHTML  

    In this paper, “tapered-Vth” buffers are explored as an approach to significantly improve the energy efficiency of traditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In addition, tapered-Vth buffers are shown to offer an up to 3× energy reduction under a given performance constraint. A circuit-level optimization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations. View full abstract»

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  • Realization Using the Fornasini-Marchesini Model for Implementations in Distributed Grid Sensor Networks

    Publication Year: 2011 , Page(s): 2708 - 2717
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    A method for distributed information processing in grid sensor networks using the Fornasini-Marchesini (FM) local state space model has been proposed in the literature recently. The method can be used to implement linear systems in grid sensor networks. It can be shown that, the system matrices of the FM state space model have to satisfy particular conditions for the system to be implementable in real time in a sensor network. This constraint limits the type of systems implementable in real time on sensor networks. A necessary and sufficient condition for a causal transfer matrix to be realizable in the constrained FM model is established. A realization algorithm to derive an FM model that satisfies the desired condition, given an admissible causal transfer matrix, is also derived. The corresponding problem for the realization of noncausal transfer matrices is also addressed. View full abstract»

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  • Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors

    Publication Year: 2011 , Page(s): 2718 - 2728
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    We present a technique for applying arbitrary invertible nonlinear functions to the internal signals of a prototype linear time-invariant digital signal processor, without causing any output disturbances. By using our proposed technique, the external input-output behavior of the DSP remains linear, and identical to that of the prototype, despite the nonlinear behavior of its internal signals. We explore the specific application of our technique to instantaneous companding, in which the introduced nonlinearities compress the dynamic range of the internal signals, so that the latter span most of the available bits in the system, thus improving the signal-to-noise-plus-distortion-ratio at the output, for low to medium input signal levels. We discuss the choice of nonlinear functions for this companding application, and we present an efficient hardware implementation for the standard 15-segment piecewise-linear approximation to the 255-μ law. We compare the performance and hardware overhead of our technique with that of other companding architectures. View full abstract»

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  • On the Cyclostationary Noise Analysis in Large RF Integrated Circuits

    Publication Year: 2011 , Page(s): 2729 - 2740
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    This paper examines the issue of noise analysis in RF integrated circuits (RFICs). The complexity of the RFIC grows constantly, with transistor counts now into the thousands or tens of thousands. Since RFICs are driven by large-signal multitone excitations, the stochastic noise process in these circuits is cyclostationary. This combination of large device count and noise cyclostationarity makes noise analysis in RFICs a time-consuming task. Simulation algorithms that minimize computer memory consumption and computation cost are thus necessary. There is a consensus now that harmonic balance is the most appropriate circuit equation solution method for multitone analysis of RF circuits. The paper thus gives a comprehensive description of a harmonic balance-based algorithm for computing the circuit noise response, showing how it effectively accounts for all types of cyclostationary noise sources supported by modern compact device models. The algorithm has been implemented in a commercial simulator and shows good capabilities for the analysis of full transceiver circuits within reasonable computer memory occupancy and simulation times. View full abstract»

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  • Parametric Lyapunov Equation Approach to Stabilization of Discrete-Time Systems With Input Delay and Saturation

    Publication Year: 2011 , Page(s): 2741 - 2754
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (605 KB) |  | HTML iconHTML  

    This paper studies the problem of stabilization of discrete-time linear systems with input delay and saturation nonlinearity. By exploring some further intricate properties of the recently developed parametric Lyapunov equation-based low-gain feedback design approach, solutions are proposed to solve the problems by both state feedback and output feedback. This new approach is not only simpler than the existing method that is based on the eigenstructure assignment technique, but also provides explicit conditions on the low-gain parameter to guarantee the stability of the closed-loop system. Moreover, it is possible by adjusting the low-gain parameter online to achieve global results when the system is subject to both input saturation and time-delay. Also, the delay in the input is allowed to be time-varying in some cases. View full abstract»

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  • Fault-Tolerant Control for Nonlinear Markovian Jump Systems via Proportional and Derivative Sliding Mode Observer Technique

    Publication Year: 2011 , Page(s): 2755 - 2764
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    This paper investigates the problem of sensor fault estimation and fault-tolerant control for Markovian jump systems with time delay and Lipschitz nonlinearities. The issues involved here are: i) sensor faults; ii) model Lipchitz nonlinearities; iii) system structure changes governed by Markovian jumping parameters; and iv) time delay in system states. Such type of mathematical models can represent a large number of practical systems in the actual engineering. A new estimation technique (named proportional and derivative sliding mode observer) is developed to deal with this design problem. The proposed observer is mode-dependent type in which a derivative gain and a proportional gain are introduced to provide more design freedom, and a discontinuous input term is introduced to eliminate the effects of sensor faults. By employing the developed estimation technique, the asymptotic estimations of system states and sensor faults can be obtained simultaneously. Based on the estimation, an observer-based fault-tolerant control scheme is developed to stabilize the resulting closed-loop system. Finally, a numerical example is presented to illustrate the effectiveness and applicability of the proposed technique. View full abstract»

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  • A Wideband Spectrum-Sensing Processor With Adaptive Detection Threshold and Sensing Time

    Publication Year: 2011 , Page(s): 2765 - 2775
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1245 KB) |  | HTML iconHTML  

    Spectrum sensing over a wide bandwidth increases the probability of finding unutilized spectrum for cognitive radios. The hardware realization of wideband sensing is challenging because strong primary users introduce large dynamic range and spectral leakage in adjacent unused bands. This paper proposes a multitap-windowed frequency power detector with adaptive threshold and sensing time to address the above challenges. The suppression of spectral leakage is achieved by multitap-windowed FFT processing, which also enables reduced sensing time. The sensing time and detection threshold are adapted according to the channel-specific spectral leakage, which results in a reliable wideband signal detection within constrained sensing time. Our simulations with a 20 dB interferer-to-noise ratio (INR) indicate a 2× improvement in detection rate compared to conventional power detectors. An order-of-magnitude improvement in sensing time is achieved in the presence of 30-dB INR interferers while maintaining a false-alarm rate of 0.1 and a detection rate of 0.9. The proposed algorithms are realized in an FPGA to demonstrate real-time operation with a latency below 10 μ s. Experimental results from a radio testbed closely match the numerical simulations. An ASIC architecture for a 200-MHz bandwidth is estimated to occupy 0.98 mm2 and dissipate 25 mW from a 1-V supply in a standard 65-nm CMOS technology. View full abstract»

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  • Design and Implementation of Software-Defined Radio Receiver Based on Blind Nonlinear System Identification and Compensation

    Publication Year: 2011 , Page(s): 2776 - 2789
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2041 KB) |  | HTML iconHTML  

    As the commonly used wideband software radio receiver does not possess the performance of a high linear dynamic range under multiple signal excitation, a new type of adaptive wideband digital receiver architecture is proposed and designed based on blind nonlinear system identification. The traditional narrowband linear receiving and channelizing technologies should not be applied to deal with the complicated multiple-signal excitation with unknown or time-varying characteristics of time domain or frequency domain. Here, the harmonic and the intermodulation components brought about by the wideband digital receiver are firstly identified and extracted in the frequency domain, then a blind identification criterion for minimizing the short-time energy of the nonlinear components is designed, and the steepest descent method (SDM) or the recursive least square (RLS) algorithm is applied to extract and update iteratively the parameters of the nonlinear behavior model of the wideband digital receiver. Finally, the updated model is utilized to compensate the nonlinear distortion of the receiver in real time. The experimental results show that the spur-free dynamic range (SFDR) of the blind identification digital receiver achieves about 20-dB higher than that of the traditional receiver under multitone or 16-QAM bandpass signal excitation. As regards the large bandwidth and the high power efficiency of the RF front end and ADC circuits, the blind identification receiver architecture is helpful for detecting weak signal in concomitance with in-band or out-of-band strong jammers. View full abstract»

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  • A Systematic USFG Design Approach for Integrated Reconfigurable Switched-Capacitor Power Converters

    Publication Year: 2011 , Page(s): 2790 - 2800
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1963 KB) |  | HTML iconHTML  

    A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load. View full abstract»

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  • Corrections to “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing” [Mar 11 507-520]

    Publication Year: 2011 , Page(s): 2801
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    In the above titled paper (ibid., vol. 58, no. 3, pp. 507-520, Mar. 2011), important missing references [2]-[5] that represent fundamental background material on compressive sensing should have been added to the reference list and included within the second paragraph of the introduction (Section I) that cites [15] and [16] in the original reference list. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2011 , Page(s): 2802
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    Publication Year: 2011 , Page(s): 2803
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    Publication Year: 2011 , Page(s): 2804
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras