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Embedded Systems Letters, IEEE

Issue 3 • Date Sept. 2011

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Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Page(s): C2
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  • Editorial Introduction of New Editor-in-Chief (EIC) and Deputy EIC

    Page(s): 73 - 74
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  • Guest Editorial Special Section on Embedded Reconfigurable Computing Systems

    Page(s): 75 - 76
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  • PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip

    Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    Adaptive multiprocessor systems are appearing as a promising solution for dealing with complex and unpredictable scenarios. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. This letter presents a novel approach based on the utilization of PI and PID controllers, widely used in control automation, for optimizing resources utilization in Multiprocessor System-on-Chip (MPSoC). Several architecture characteristics such as response time during frequency changing, noise and perturbations are modeled and validated in a high-level model and results are compared to information obtained on a homogeneous MPSoC platform prototype. Power and energy consumption figures are discussed and two controllers are proposed: 1) PI-; and 2) PID-based controllers. Results show the system capability of adapting under disturbing conditions while ensuring application performance constraints and reducing energy consumption. View full abstract»

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  • Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation

    Page(s): 81 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (210 KB) |  | HTML iconHTML  

    Field-programmable gate arrays (FPGAs) suffer from lower application design productivity than other devices, which is largely due to compilation taking hours or even days. Making FPGA compilation comparable to software compilation is critical for continued FPGA usage due to competitive technologies, such as graphics-processing units, that use languages with runtime compilation models. In this letter, we evaluate virtual reconfigurable architectures, referred to as intermediate fabrics, which enable near-instant placement and routing of applications for commercial FPGAs. View full abstract»

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  • Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems

    Page(s): 85 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    This letter presents efficient and modular task scheduler and allocator support for dynamically and partially reconfigurable electronic systems. This enables hardware tasks to be preempted and arbitrarily placed at an optimal position on the chip on-the-fly. In particular, we present a novel fault-tolerant allocating algorithm called “best-fit empty area compact (BF-EAC),” and its on-chip implementation on a Xilinx Virtex-4 field-programmable gate array (FPGA), which circumvents emerging faults while maintaining more compact empty areas for emerging tasks. We also present an implementation of the early deadline first (EDF) scheduling heuristic used to optimize the chronological order of execution of hardware tasks to meet real time constraints. Put together, the placement and scheduling architecture efficiently exploits chip resources with a μs-grade computing speed and a lightweight footprint (less than 500 slices). View full abstract»

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  • A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems

    Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    As the size of integrated circuits has reached the nanoscale, embedded memories are more sensitive to single-event upsets (SEUs) or double-event upsets (DEUs), due to their low threshold voltage. In particular, reconfigurable systems, containing a large number of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEUs and DEUs. In this letter, we develop a Hamming code based error detection and correction (EDAC) circuit that can protect the configuration memory of a reconfigurable device from SEUs. Evaluation reveals that compared to the conventional triple modular redundancy (TMR) protected field-programmable gate array (FPGA) tile, the proposed EDAC protected FPGA tile shows about 2.3 times better dependability on the influence of DEUs. Moreover, as the FPGA array size increases, the dependability advantage of EDAC increases exponentially. The main drawback of EDAC is that it has about 1.6 times greater area overhead than TMR. View full abstract»

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  • Scheduling Conditions for Real-Time Software Transactional Memory

    Page(s): 93 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (666 KB) |  | HTML iconHTML  

    Software transactional memory (STM) is a transactional mechanism of controlling access to shared resources in memory. Recently, variants of STM with real-time support have been presented. Due to its abort-restart nature, the execution semantics of STM are different from the classical preemptive or nonpreemptive model. In this letter, we formally derive utilization based necessary and sufficient scheduling condition for a STM system using lazy conflict detection. View full abstract»

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  • A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs

    Page(s): 97 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    Integrating more functionality in a smaller form factor with higher performance and lower power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. This letter introduces a TSV-aware partitioning algorithm that enables higher performance for application implementation onto 3-D field-programmable gate arrays (FPGAs). Unlike other algorithms that minimize the number of connections among layers, our solution leads to a more efficient utilization of the available (fabricated) interlayer connectivity. Experimental results show average reductions in delay and power consumption, as compared to similar 3-D computer-aided design (CAD) tools, about 28% and 26%, respectively. View full abstract»

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  • Special issue on novel memory architecture and organization

    Page(s): 101
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    Page(s): 102
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    Page(s): 103
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  • Advertisement - Why we joined

    Page(s): 104
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  • IEEE Embedded Systems Letters Information for authors

    Page(s): C3
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  • Blank page [back cover]

    Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo