# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 69

Publication Year: 2011, Page(s):C1 - 3651
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2011, Page(s): C2
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• ### The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps

Publication Year: 2011, Page(s):3652 - 3666
Cited by:  Papers (197)
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One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reactio... View full abstract»

• ### An Extraction Method of the Energy Distribution of Interface Traps by an Optically Assisted Charge Pumping Technique

Publication Year: 2011, Page(s):3667 - 3673
Cited by:  Papers (4)
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The energy distribution of interface traps is extracted using an optically assisted charge pumping (optical CP) technique. Optically generated majority carriers through light illumination enable the CP process even in a floating-body (FB) device without an extra body contact. With the use of square pulses at different rising and falling times and the proposed analytical model, the energy distribut... View full abstract»

• ### Gate-First Metal-Gate/High-$k$ n-MOSFETs With Deep Sub-nm Equivalent Oxide Thickness (0.58 nm) Fabricated With Sulfur-Implanted Schottky Source/Drain Using a Low-Temperature Process

Publication Year: 2011, Page(s):3674 - 3677
Cited by:  Papers (3)
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Gate-first high-k/metal-gate n-MOSFETs with a deep subnanometer (sub-nm) equivalent oxide thickness (EOT) of 0.58 nm were successfully fabricated with Schottky source/drain contacts using a low-temperature process. The key to achieving such a thin EOT is the use of a low-temperature process for the NiSi Schottky source/drain formation. A sulfur implantation technique was used to overcome th... View full abstract»

• ### A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

Publication Year: 2011, Page(s):3678 - 3686
Cited by:  Papers (3)  |  Patents (1)
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For more than 45 years, photon- and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection ... View full abstract»

• ### Physical and Electrical Performance Limits of High-Speed SiGeC HBTs—Part I: Vertical Scaling

Publication Year: 2011, Page(s):3687 - 3696
Cited by:  Papers (42)
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The overall purpose of this paper (including Part I, in this issue) is the prediction of the ultimate electrical high-frequency performance potential for SiGeC heterojunction bipolar transistors under the constraints of practical applications. This goal is achieved by utilizing most advanced device simulation tools with parameters calibrated to existing experimental results. This Part I outlines t... View full abstract»

• ### Physical and Electrical Performance Limits of High-Speed Si GeC HBTs—Part II: Lateral Scaling

Publication Year: 2011, Page(s):3697 - 3706
Cited by:  Papers (3)
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The overall purpose of this paper is the prediction of the ultimate electrical high-frequency performance potential for SiGeC HBTs under the constraints of practical applications. This goal is achieved by utilizing advanced device simulation tools with parameters calibrated to experimental results of most advanced existing technologies. In addition, detailed electrostatic and electrothermal simula... View full abstract»

• ### A Statistical Model of Erratic Behaviors in Flash Memory Arrays

Publication Year: 2011, Page(s):3707 - 3711
Cited by:  Papers (9)
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We present a statistical model of erratic behaviors in Flash memory arrays based on a Markov chain model. The model parameters are experimentally evaluated through short-program/erase-cycling characterizations. The model is suitable for Monte Carlo simulations of Flash memory arrays through which the presence of tail bits in the threshold voltage distribution can be correctly predicted. Finally, a... View full abstract»

• ### Analysis of the Correlation Between the Programmed Threshold-Voltage Distribution Spread of nand Flash Memory Devices and Floating-Gate Impurity Concentration

Publication Year: 2011, Page(s):3712 - 3719
Cited by:  Papers (6)
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The effect of the activated floating-gate (FG) impurity concentration on the programmed threshold-voltage ( Vt) distribution was newly investigated and analyzed. The lower FG impurity concentration leads to a wider threshold-voltage distribution, which is explained by the time-dependent tunnel-oxide electric-field enhancement effect induced by the reduction of the depletion regio... View full abstract»

• ### On-Chip High-Performance Millimeter-Wave Transmission Lines on Locally Grown Porous Silicon Areas

Publication Year: 2011, Page(s):3720 - 3724
Cited by:  Papers (19)
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High-performance on-chip coplanar-waveguide (CPW) transmission lines (TLs) were fabricated on locally formed porous silicon membranes on the Si wafer, and their millimeter-wave (mmW) characteristics were measured up to 110 GHz. It was demonstrated that a quality factor three times higher than that of conventional CPWs fabricated in standard CMOS on bulk crystalline Si can be obtained in mmW freque... View full abstract»

• ### An Analytical Model for Line-Edge Roughness Limited Mobility of Graphene Nanoribbons

Publication Year: 2011, Page(s):3725 - 3735
Cited by:  Papers (17)
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The electronic properties of graphene nanoribbons (GNRs) in the presence of line-edge roughness scattering are studied. The mobility, conductivity, mean free path, and localization length of carriers are analytically derived using an effective mass model for the band structure. This model provides a deep insight into the operation of armchair GNR devices in the presence of line-edge roughness. The... View full abstract»

• ### TiN Metal Gate Electrode Thickness Effect on BTI and Dielectric Breakdown in HfSiON-Based MOSFETs

Publication Year: 2011, Page(s):3736 - 3742
Cited by:  Papers (6)
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Effects of a TiN gate electrode on interface trap density, bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB) in HfSiON metal-oxide-semiconductor field-effect transistors are investigated in this paper. Based on experimental data, we found that the TiN metal gate electrode thickness plays an important role in determining the final dielectric stability and the interf... View full abstract»

• ### Electrical Performance Optimization of Nanoscale Double-Gate MOSFETs Using Multiobjective Genetic Algorithms

Publication Year: 2011, Page(s):3743 - 3750
Cited by:  Papers (21)
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In this paper, a new multiobjective genetic algorithm (MOGA)-based approach is proposed to optimize the electrical performance of double-gate (DG) MOSFETs for nanoscale CMOS digital applications. The proposed approach combines the universal optimization and fitting capability of MOGAs and the cost-effective optimization concept of quantum correction to achieve reliable and optimized designs of DG ... View full abstract»

• ### An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

Publication Year: 2011, Page(s):3751 - 3758
Cited by:  Papers (18)
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The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implante... View full abstract»

• ### Extended Analysis of Capacitance–Voltage Curves for the Determination of Bulk Dopant Concentrations of Textured Silicon Solar Cells

Publication Year: 2011, Page(s):3759 - 3770
Cited by:  Papers (3)
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Capacitance-Voltage (C- V) measurements are an established method for determining the bulk dopant concentration Nbulk of semiconductor devices. The extraction of Nbulk requires knowledge of the surface area of the space-charge region (SCR). For textured solar cells, this surface area is enlarged, depending on texture and bias voltage. The amount of... View full abstract»

• ### Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices

Publication Year: 2011, Page(s):3771 - 3777
Cited by:  Papers (5)
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This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the am... View full abstract»

• ### Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation

Publication Year: 2011, Page(s):3778 - 3786
Cited by:  Papers (10)
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Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface and higher thermal stability. The impact of Pt incorporation is widely accepted and recognized in research field; however, the role of Pt in NiSi films has not been fully clarified so far. In this paper, the spatial distributions of Pt ... View full abstract»

• ### Improvement in off-State Leakage Current of n-Channel SOS MOSFETs by Hydrogen Annealing of the SOS Film

Publication Year: 2011, Page(s):3787 - 3792
Cited by:  Papers (3)
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The off-state source-to-drain leakage current and punchthrough voltage are the quantities that frequently limit the performance of short-channel floating-body silicon-on-sapphire (SOS) n-channel MOSFETs. In this paper, we demonstrate that the high-temperature hydrogen annealing of the SOS film prior to the device fabrication leads to marked improvement in these two parameters. The effect is attrib... View full abstract»

• ### Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

Publication Year: 2011, Page(s):3793 - 3800
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In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the tra... View full abstract»

• ### NiGe Contacts and Junction Architectures for P and As Doped Germanium Devices

Publication Year: 2011, Page(s):3801 - 3807
Cited by:  Papers (9)  |  Patents (3)
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In this paper, the contact resistivity of NiGe on n-doped Ge is extracted. Although phosphorus is the slowest n-type dopant in terms of diffusion in Ge, the corresponding contact resistivity data for this dopant are sparse. Contact resistivity dependence on implant dose will be determined, as well as a comparison of phosphorus- and arsenic-doped Ge layers. The impact of high contact resistance is ... View full abstract»

• ### Scaling Between Channel Mobility and Interface State Density in SiC MOSFETs

Publication Year: 2011, Page(s):3808 - 3811
Cited by:  Papers (49)
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The direct impact of the SiO2/4H-SiC interface state density (Dit) on the channel mobility of lateral field-effect transistors is studied by tailoring the trap distribution via nitridation of the thermal gate oxide. We observe that mobility scales like the inverse of the charged state density, which is consistent with Coulomb-scattering-limited transport at the interfa... View full abstract»

• ### Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors

Publication Year: 2011, Page(s):3812 - 3819
Cited by:  Papers (4)
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SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to expla... View full abstract»

• ### Three-Dimensional Integration Approach to High-Density Memory Devices

Publication Year: 2011, Page(s):3820 - 3828
Cited by:  Papers (14)  |  Patents (5)
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The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically a... View full abstract»

• ### Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs

Publication Year: 2011, Page(s):3829 - 3836
Cited by:  Papers (13)
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Uniaxial strain effects on electron ballistic transport in extremely scaled gate-all-around nanowire MOSFETs with both [100] and [110] orientations are investigated in this paper. Band structures of nanowires without and with strain are calculated using the empirical sp3d5s* tight-binding model. The top-of-the-barrier model is utilized to simulate the electron ballistic trans... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy