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Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2011

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Displaying Results 1 - 21 of 21
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
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  • Editorial from the Outgoing Editor-in-Chief

    Page(s): 477
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  • Editorial

    Page(s): 478 - 479
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  • Max Separation Clustering for Feature Extraction From Optical Emission Spectroscopy Data

    Page(s): 480 - 488
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB) |  | HTML iconHTML  

    This paper proposes max separation clustering (MSC), a new non-hierarchical clustering method used for feature extraction from optical emission spectroscopy (OES) data for plasma etch process control applications. OES data is high dimensional and inherently highly redundant with the result that it is difficult if not impossible to recognize useful features and key variables by direct visualization. MSC is developed for clustering variables with distinctive patterns and providing effective pattern representation by a small number of representative variables. The relationship between signal-to-noise ratio (SNR) and clustering performance is highlighted, leading to a requirement that low SNR signals be removed before applying MSC. Experimental results on industrial OES data show that MSC with low SNR signal removal produces effective summarization of the dominant patterns in the data. View full abstract»

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  • Metrology Sampling Strategies for Process Monitoring Applications

    Page(s): 489 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    Shrinking process windows in very large scale integration semiconductor manufacturing have already necessitated the development of control systems capable of addressing sub-lot-level variation. Within-wafer control is the next milestone in the evolution of advanced process control from lot-based and wafer-based control. In order to adequately comprehend and control within-wafer spatial variation, inline measurements must be performed at multiple locations across the wafer. At the same time, economic pressures prompt a reduction in metrology, for both capital and cycle-time reasons. This paper explores the use of modeling and minimum-variance prediction as a method to select the sites for measurement on each wafer. The models are developed using the standard statistical tools of principal component analysis and canonical correlation analysis. The proposed selection method is validated using real manufacturing data, and results indicate that it is possible to significantly reduce the number of measurements with little loss in the information obtained for the process control systems. View full abstract»

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  • Enabling Scatterometry as an In-Line Measurement Technique for 32 nm BEOL Application

    Page(s): 499 - 512
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1569 KB) |  | HTML iconHTML  

    Conventional metrology tools are unable to precisely monitor some interconnect attributes such as trench sidewall angle either due to limited capability or excessive cycle time. But these attributes have great impact on interconnect performance for 32 nm technology node and beyond. Scatterometry, a non-destructive metrology technique, is proposed to address the shortcomings of current metrology tools while also potentially providing additional measurement capabilities that enable more comprehensive characterization of interconnect attributes. Enabling scatterometry for back-end-of-line metrology at 32 nm technology node is challenged by the inherent complexity of a multilayer film structure. The research reported describes the implementation of scatterometry measurements to explore the advantages of this technique for the 32 nm technology node. The results obtained demonstrate the superiority of scatterometry techniques over conventional semiconductor metrology tools such as throughput, process control capability, precision, and accuracy. The total measurement uncertainty of scatterometry results with tunneling electron microscope and cross-sectional scanning electron microscope results for line height shows 1.92 and 6.46 nm, respectively, which compare favorably to the reference metrology tools. Scatterometry techniques also exhibited impressive potential to estimate end-of-the-line electrical parametric data. Finally, physical dimensions obtained from scatterometry measurements are shown to be comparable to TEM results from product wafers. View full abstract»

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  • Study of Bubble Activity in a Megasonic Field Using an Electrochemical Technique

    Page(s): 513 - 518
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    In the megasonic cleaning of wafers, size and motion of cavitating bubbles and fluid flow due to acoustic streaming play a very important role. In this paper, chronoamperometric technique has been used to seek information on acoustic streaming and bubble activity in a 1 MHz sound field. Specifically, current transients during reduction of potassium ferricyanide were recorded. Data collected at 1-6 MHz sampling rate using a 25 μm platinum electrode show current “peaks” indicative of the approach of oscillating bubbles to the electrode and current “valleys” due to blocking of the electrode by bubbles. Acoustic streaming velocity ( ~ 1.5 cm/s) and bubble size (maximum radius of ~ 1 μm for oscillating bubbles) have been estimated from local current transients caused by bubble activity near the electrode. View full abstract»

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  • Spectral Evidence of Si Complexes in HVPE-Grown GaAs

    Page(s): 519 - 522
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    Evidence of Si complexes was discovered in low temperature photoluminescence (PL) spectra recorded from GaAs grown by hydride vapor phase epitaxy and were measured as a function of secondary HCl flow. In addition, time resolved PL of the samples measured long radiative lifetimes, substantiating the excellent quality of the crystalline growth. View full abstract»

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  • Nonlinear Sequential Bayesian Analysis-Based Decision Making for End-Point Detection of Chemical Mechanical Planarization (CMP) Processes

    Page(s): 523 - 532
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    Chemical mechanical planarization (CMP) process has been widely used in the semiconductor manufacturing industry for realizing highly polished (surface roughness Ra ~1 nm ) and planar [WIWNU ~ 1%, thickness variation standard deviation ~3 nm] surfaces of an in-process wafer. In CMP, accurate and timely decisions for end-point detection (EPD) are extremely important to enable the process to effectively respond to demand variations and disruptions. In this paper, we apply nonlinear sequential Bayesian analysis and decision theory to establish a quantitative relationship that connects the features (inputs) extracted from on-line wireless vibration sensor signals with the process performance measures, such as material removal (outputs) for EPD in copper CMP process. A case study with actual CMP data is provided to demonstrate the effectiveness of the present approach. Note to practitioners. The semiconductor industry widely uses CMP process for realizing highly polished planar surfaces on inter-level dielectrics and metallic interconnects in the fabrication of integrated circuits. Accurate and timely detection of the end-point (EPD) of the CMP process is critical to prevent over-polishing or under-polishing of wafer surfaces, and thus meet the wafer yield requirements under growing demands on wafer density and performance. An EPD system uses information from in-process sensors and/or inspection instruments to facilitate decisions on when to stop the polishing process, and adjust process settings for optimal performance. However, the issue of developing cost-effective sensors, and addressing the uncertainty in the sensor information remains a challenge. We have developed an EPD system based on deriving and sequentially updating a cost-function using the uncertain information from wireless MEMS vibration sensors mounted on a CMP apparatus. Decisions on EPD are made based on optimizing the updated cost function at every time-step. Our experimental investigations suggest th- - at the sensor information can be effectively used for implementing EPD, and it can minimize the costs of over-polishing and under-polishing of wafers during CMP process. As part of future work, we are investigating the robustness of the EPD system to different forms of uncertainty in the sensor information, and much wider configurations of sensors and CMP setups. View full abstract»

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  • Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

    Page(s): 533 - 544
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (617 KB) |  | HTML iconHTML  

    With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4× less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1 V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications. View full abstract»

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  • Uniform, Low-Resistive Ni-Pt Silicide Fabricated by Partial Conversion With Low Metal-Consumption Ratio

    Page(s): 545 - 551
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    We applied partial conversion (PC) with a low metal-consumption ratio (MCR) as the initial silicidation, fabricating uniform and low-resistive Ni-Pt silicide regardless of the device patterns across a wafer. The key to PC in Ni-Pt silicidation was leaving the Ni-Pt alloy on the silicide after the initial silicidation. This process enriched the Pt of the Ni-Pt silicide because the Pt was supplied from the unconsumed Ni-Pt alloy on the silicide during the initial silicidation. The resistivity of Ni-Pt silicide was as low as that of NiSi at MCRs of less than 80%, suppressing the formation of nickel di-silicide (NiSi2) on the even narrow active line. We concluded that Pt on the silicide/Si interface and the grain boundaries of silicides can restrain Ni diffusion toward the <;110>; direction into the Si substrate, which suppresses the formation of NiSi2. View full abstract»

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  • Wafer Surface Charging Model for Single-Wafer Wet-Spin Processes

    Page(s): 552 - 558
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    Wet chemical processes in integrated circuit (IC) manufacturing are used in many applications, e.g., post-etch residue removal and pre-deposition surface treatment. While advanced single-wafer wet spin tools are part of the critical tool-set for advanced IC fabrication, non-optimized tool hardware and/or process may induce different types of wafer surface charging issues. In this paper, a physical model to fundamentally explain surface charging induced by a single-wafer wet spin tool is described. The model is based on the advection of surface charges from wafer-center to wafer-edge resulting from the shear flow of the liquid. The charge distribution in the diffuse layer adjacent the wafer surface is calculated by solving the coupled Poisson's and current continuity equations. As often practiced in the industry in characterizing this type of wafer surface charging, a thermally grown silicon dioxide surface is used as the model surface and de-ionized water as the liquid medium. Good agreement is obtained between experimental and calculated surface charging potentials for radial positions extending from wafer-center to approximately 130 mm on standard 300 mm diameter wafers. The observed charging potential trends with respect to radial position, wet process time, and wafer spin speed are well explained by the current model. View full abstract»

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  • Physical Model for the Small-Scale Residual Topography in Chemical Mechanical Polishing

    Page(s): 559 - 565
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    In previous work, the small-scale topography evolution of the wafer surface was investigated for a typical interlevel dielectric chemical mechanical planarization process by means of a Fourier analysis of surface profiler scans. It was found that the amplitudes of the individual frequency components decay exponentially at a rate that depends on the respective spatial frequency. In this paper, a physical model of these findings is proposed, based on a linearized approximation of the Greenwood-Williamson approach to describe the contact between the pad and the wafer surface. The frequency dependency of the decay rates is attributed to the visco-elastic properties of the pad material (polyurethane). This connection is consistent with dielectric susceptibility measurements that show that the observed frequency dependency stems from a visco-elastic beta-transition in polyurethane. The resulting model not only describes the experimental data for a previous test pattern but also shows good agreement to measurements of a typical dynamic random access memory topography after chemical mechanical polishing. In addition, the current model reduces the systematic errors of the predicted topography as compared to the previous empirical model. View full abstract»

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  • 2011 IEEE International Electron Devices Meeting (IEDM)

    Page(s): 566
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  • 2012 IEEE International Reliabilty Physics Symposium (IRPS)

    Page(s): 567
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  • Thirteenth IEEE International Vacuum Electronics Conference and Ninth IEEE International Vacuum Electron Sources Conference (IVEC-IVESC 2012)

    Page(s): 568
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  • IEEE EnergyTech 2012

    Page(s): 569
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  • 2011 Index IEEE Transactions on Semiconductor Manufacturing Vol. 24

    Page(s): 570 - 584
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Page(s): C3
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  • Blank page [back cover]

    Page(s): C4
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721