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Solid-State Circuits, IEEE Journal of

Issue 10 • Date Oct. 2011

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Displaying Results 1 - 25 of 27
  • [Front cover]

    Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 2189 - 2190
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  • Introduction to the Special Section on the 32nd Annual IEEE Compound Semiconductor Integrated Circuit Symposium

    Page(s): 2191 - 2192
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  • Metamorphic HEMT MMICs and Modules Operating Between 300 and 500 GHz

    Page(s): 2193 - 2202
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    In this paper, we present the development of submillimeter-wave monolithic integrated circuits (S-MMICs) and modules for use in next-generation sensors and high-data-rate wireless communication systems, operating in the 300-500-GHz frequency regime. A four-stage 460-GHz amplifier MMIC and a 440-GHz class-B frequency doubler circuit have been successfully realized using our 35-nm InAlAs/InGaAs-based metamorphic high-electron mobility transistor (mHEMT) technology in combination with grounded coplanar circuit topology (GCPW). Additionally, a 500-GHz amplifier MMIC was fabricated using a more advanced 20-nm mHEMT technology. To package the submillimeter-wave circuits, a set of waveguide-to-microstrip transitions has been fabricated on both 50-μm-thick quartz and GaAs substrates, covering the frequency range between 220 and 500 GHz. The E-plane probes were integrated in a four-stage 20-nm cascode amplifier circuit to realize a full H -band (220 to 325 GHz) S-MMIC amplifier module with monolithically integrated waveguide transitions. View full abstract»

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  • InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz

    Page(s): 2203 - 2214
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    We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz. View full abstract»

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  • Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

    Page(s): 2215 - 2225
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    This paper presents the circuit designs and measured performance of two ultrahigh-speed low-power 6-b digital-to-analog converters (DACs) using InP-based heterojunction bipolar transistors (HBTs) for beyond-100-Gb/s/ch optical transmission systems. The first design is based on an R-2R ladder-based current-steering architecture with a novel double-sampling technique that relaxes the speed restraints for the DAC and helps achieve ultrahigh-speed operation. The DAC with the double-sampling technique achieves an excellent sampling speed of up to 32 GS/s with low power consumption of 1.4 W. The second design is based on a new timing alignment technique. The DAC with the timing alignment technique operates at a sampling rate of 28 GS/s with very low power consumption of 0.95 W and achieves an excellent figure of merit (0.53 pJ per conversion step). It provides a clear multilevel modulated signal for QAM transmission and can be applied to beyond-100-Gb/s/ch optical transmission systems. View full abstract»

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  • A 2.4- \hbox {V} _{\rm pp} 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies

    Page(s): 2226 - 2239
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    The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50-Ω output transmission line. The DA features digital variable gain amplifier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at three different peaking frequencies. Binary-weighted MOSFET gate-finger groupings are employed in a Gilbert-cell based DVGA topology to minimize bit-dependent output impedance and group delay variations. S -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than -10 dB up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s. Equalization experiments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz. View full abstract»

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  • Design and Analysis of a W-Band SiGe Direct-Detection-Based Passive Imaging Receiver

    Page(s): 2240 - 2252
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    A W-band direct-detection-based receiver front-end for millimeter-wave passive imaging in a 0.18-μm BiCMOS process is presented. The proposed system is comprised of a direct-detection front-end architecture employing a balanced LNA with an embedded Dicke switch, power detector, and baseband circuitry. The use of a balanced LNA with an embedded Dicke switch minimizes front-end noise figure, resulting in a great imaging resolution. The receiver chip achieves a measured responsivity of 20-43 MV/W with a front-end 3-dB bandwidth of 26 GHz, while consuming 200 mW. The calculated NETD of the SiGe receiver chip is 0.4 K with a 30 ms integration time. This work demonstrates the possibility of silicon-based system-on-chip solutions as lower cost alternatives to compound semiconductor multi-chip imaging modules. View full abstract»

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  • Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

    Page(s): 2253 - 2267
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    A robust digitally assisted self-calibration technique is presented to improve the input-referred second-order-intermodulation intercept point (IIP2) of direct-conversion receivers. The low-power, low-noise 1.8-GHz CMOS receiver prototype relies on digital signal processing to improve analog/RF performance with only a minimum hardware overhead and with no performance penalties on the RF front end and analog baseband. The RF front end achieves an IIP2 better than 60 dBm without external filters between the LNA and downconversion mixers, has a conversion gain of 38.5 dB, a low DSB noise figure of 2.6 dB, and an IIP3 of -17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm2 on a 0.13-μm CMOS process. View full abstract»

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  • An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS

    Page(s): 2268 - 2283
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    We present an ultra-low voltage, highly linear, low noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates programmable, in-band feed-forward interferer cancellation at the baseband to obtain high linearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally calibrated interferer cancellation improves the IIP3 and IIP2 by more than 13 dB and 8 dB respectively with very little impact on the receiver noise figure. As such, it breaks the trade-off between linearity and noise figure, making it possible to use a high-gain RF front-end to achieve low noise figure without affecting the linearity of the ultra-low voltage baseband circuits. The 0.6-V 900-MHz direct-conversion receiver prototype integrates a differential LNA, RF transconductors, linear quadrature current driven passive mixers, feed-forward interferer cancellation circuits, baseband variable gain transimpedance amplifiers and second-order channel-select filters. It has a nominal conversion gain of 56.4 dB, noise figure of 5 dB, IIP3 of -9.8 dBm and IIP2 of 21.4 dBm. The receiver operates reliably from 0.55-0.65 V, consumes 26.4 mW and occupies an active area of 1.7 mm2 in a 65-nm low-power CMOS process, of which the feed-forward interferer cancellation circuits consume 11.4 mW and occupies 0.43 mm2 . View full abstract»

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  • An Ultra-Wideband Impulse-Radio Transceiver Chipset Using Synchronized-OOK Modulation

    Page(s): 2284 - 2299
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    This work presents a low-complexity IR-UWB chipset which achieves synchronization and demodulation at the receiver relying only on a ring oscillator clock. The modulation scheme used, synchronized-OOK (S-OOK), permits low power timing acquisition and data reception with a static CMOS digital synchronizer and demodulator counting 61 logic elements. The receiver consists of a modified energy detector (ED) that allows to asynchronously receive UWB pulses in presence of narrowband interference (NBI) with power levels up to -5 and -16 dBm for 5.4 and 2.4 GHz continuous wave interfering signals respectively. The sensitivity is -60/ -66 dBm with an overall energy dissipation of 2.9/3.9 nJ/bit for a 1 Mbps S-OOK PRBS data stream and a 100% power duty cycle. The complete demodulation and synchronization digital back-end consumes only 0.2 mW (including on-chip output buffers) during normal operation. The IR-UWB transmitter is based on a gated LC oscillator and achieves pulse durations of ~2 ns for bandwidths of 500 MHz. It consumes 249 pJ/bit energy per bit at 1 Mbps OOK. View full abstract»

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  • A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology

    Page(s): 2300 - 2311
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    A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the HSYNC. Otherwise, the displayed image will become blurry. A fast phase tracking all-digital PLL (ADPLL) for video pixel clock generation in a 65 nm CMOS technology is presented in this paper. In the proposed ADPLL, the digital loop filter eliminates the reference clock jitter effects and then the period jitter of the output pixel clock can be reduced. A time-to-digital converter (TDC) and a delta-sigma modulator (DSM) are used to perform the fast phase tracking, and the tracking jitter is controlled at less than one-third of the output pixel clock period. As compared to prior studies, the proposed ADPLL does not require an extra external oscillator to overcome the reference clock jitter effects. Thus, it has a small chip area and low power consumption, and is well-suited to video pixel clock generation applications in 65 nm CMOS process. View full abstract»

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  • A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

    Page(s): 2312 - 2325
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    A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 μm × 105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing. View full abstract»

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  • A 0.6-V 82-dB 28.6- \mu W Continuous-Time Audio Delta-Sigma Modulator

    Page(s): 2326 - 2335
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    The design of a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented in this paper for audio applications. The modulator employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to low-voltage operation and low-power consumption. The energy efficiency is further improved by embedding the summation of feedforward paths into the quantizer. For low-voltage operation, a gain-enhanced fully-differential amplifier and a body-driven rail-to-rail input CMFB circuit are developed. The modulator, implemented in a 0.13-μm standard CMOS technology with a core area of 0.11 mm2, achieves an 82-dB dynamic range (DR), and a 79.1-dB peak signal-to-noise and distortion ratio (SNDR) over a 20-kHz signal bandwidth. The power consumption of the modulator is 28.6 μW under a 0.6-V supply voltage. The achieved performance make it one of the best among state-of-the-art sub-1-V modulators in terms of two widely used figures of merit. View full abstract»

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  • Design and Analysis of a Self-Oscillating Class D Audio Amplifier Employing a Hysteretic Comparator

    Page(s): 2336 - 2349
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    A third-order self-oscillating class D audio amplifier that utilizes a hysteretic comparator is presented. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7 μm CMOS process. It achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8 Ω load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W . The area of the amplifier is 6 mm2 . View full abstract»

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  • A Wide-Load-Range Constant-Charge-Auto-Hopping Control Single-Inductor-Dual-Output Boost Regulator With Minimized Cross-Regulation

    Page(s): 2350 - 2362
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    A novel single-inductor-dual-output (SIDO) boost regulator with sequential-control is presented. This control can handle large loads or unbalanced loads with minimized cross interference between channels. A constant-charge-auto-hopping (CCAH) control is also presented to further extend the power handling capacity of the regulator with a predictable system switching noise spectrum. The switching frequency of the converter can be automatically hopped between 1 MHz and 1 MHz/N where N = 2 to 7 according to the total loads and during load transient. To minimize cross-regulation during frequency hopping, the inductor peak current is set to a predefined value according to the switching frequency information from the frequency detection unit to deliver a constant charge per switching period to the unchanged outputs. The response of the transient output is also enhanced with this inductor peak current prediction method. A prototype has been fabricated with a 0.35 μm CMOS process to verify the effectiveness of the CCAH control. With 1.8 V-2.4 V input voltage, two regulated output voltages between 3.0 V and 3.6 V, with maximum 400 mA to 600 mA driving capability and maximum power efficiency of 91.6% is achieved at total output power of 1.15 W. Load transient measurements show that the worst-case cross-regulation is 0.033 mV/mA with a 300 mA load current change at output A and 0.0714 mV/mA with a 280 mA load current change at output B. No noticeable cross-regulation can be observed with a less than 200 mA load current change. View full abstract»

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  • A Scalable Massively Parallel Processor for Real-Time Image Processing

    Page(s): 2363 - 2373
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    This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm2 . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices. View full abstract»

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  • An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization

    Page(s): 2374 - 2385
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    Variations in the number and characteristics of charges or traps contributing to transistor degradation lead to a distribution of device “ages” at any given time. This issue is well understood in the study of time dependent dielectric breakdown, but is just beginning to be thoroughly addressed under bias temperature instability (BTI) and hot carrier injection (HCI) stress. In this paper, we present a measurement system that facilitates efficient statistical aging measurements involving the latter two mechanisms in an array of ring oscillators. Microsecond measurements for minimal BTI recovery, as well as frequency shift measurement resolution ranging down to the error floor of 0.07% are achieved with three beat frequency detection systems working in tandem. Measurement results from a 65 nm test chip show that fresh frequency and the stress-induced shift are uncorrelated, both the mean and standard deviation of that shift increase with stress, and the standard deviation/mean ratio decreases with stress time. View full abstract»

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  • Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing

    Page(s): 2386 - 2395
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    A capacitively coupled probing circuit with a novel de-skewer, a low-pass filter and a high-sensitivity receiver is proposed to realize a membrane-based wafer-level simultaneous testing robustly. The de-skewer can be designed by only digital core transistors and has stable feed-forward architecture. The receiver with the low-pass filter can suppress the undesirable ringing caused by the complex wiring structure in the probe card. A probe chip and a 300 mm DUT-wafer are fabricated in a 1.2 V 90 nm technology and the measured power consumption of RX core is 0.5 mW at 1 Gbps operation. The BER is improved below 10-12 over almost all UI range when the de-skewing function is turned on. View full abstract»

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  • Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

    Page(s): 2396 - 2405
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    In this paper, a simultaneous body and word-line biasing control scheme is described for minimizing the cell leakage current in DRAMs. In the proposed biasing scheme, both the reverse body and negative word-line bias voltages are simultaneously controlled in real time by monitoring the leakage current of a group of replica DRAM cells in different leakage conditions. Experimental results in a 46 nm DRAM technology indicated that the data retention time provided by the proposed scheme is improved by up to 60% as compared to the conventional fixed biasing scheme. They also indicated that the number of failure bits of a DRAM array was substantially reduced by adopting the proposed scheme. View full abstract»

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  • A 0.5 V Operation V _{\rm TH} Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems

    Page(s): 2406 - 2415
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    A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage (VDD) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on VDD. When the 0.5 V VDD is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the VTH variation. DRAM has a potential to operate at such low VDD. As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 μm standard CMOS process and the high-speed boosting is experimentally demonstrated. View full abstract»

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  • A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy

    Page(s): 2416 - 2430
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    An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques. View full abstract»

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  • 5T SRAM With Asymmetric Sizing for Improved Read Stability

    Page(s): 2431 - 2442
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    Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due to a complex trade-off space involving stability, performance, power, and area. Local and global variation make SRAM design even more challenging. We present a 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and to provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare the 5T with the conventional 6T and the 8T and show how it can be a flexible, intermediate alternative between the two. We also investigate single-ended sensing for the 5T. Finally, we present measurement results in a 45 nm test chip that demonstrate the functionality of the 5T. Through a combination of write assists, the 5T can demonstrate comparable writability down to 0.7 V, while showing no read errors down to 0.5 V. View full abstract»

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  • Call for Fellow nominations

    Page(s): 2443
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan