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IEEE Transactions on Circuits and Systems II: Express Briefs

Issue 9 • Date Sept. 2011

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2011, Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2011, Page(s): C2
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  • A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels

    Publication Year: 2011, Page(s):545 - 549
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB) | HTML iconHTML

    Various forms of discontinuities such as stubs, vias, and wire bonds can result in deep amplitude notches in wireline channels. The data rate for systems operating using such channels, in the absence of a power-hungry decision-feedback equalizer (DFE), is limited by the lowest notch frequency of the channel. This brief proposes a multiband transceiver system to overcome this limitation by upconver... View full abstract»

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  • A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

    Publication Year: 2011, Page(s):550 - 554
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (766 KB) | HTML iconHTML

    Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is presented, where the supply voltage of 1.0 V is employed. The divider achieves a full modulus range from 1 to 256 and operates over a wide range maintaining up to 4 GHz with -30-dBm input power. The divider also accomplishes a pow... View full abstract»

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  • A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

    Publication Year: 2011, Page(s):555 - 559
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filter's auto-zeroing operation. The... View full abstract»

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  • A Jitter and Power Analysis on DCO

    Publication Year: 2011, Page(s):560 - 564
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB) | HTML iconHTML

    A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DC... View full abstract»

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  • Injection-Locking-Based Power and Speed Optimization of CML Dividers

    Publication Year: 2011, Page(s):565 - 569
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (561 KB) | HTML iconHTML

    In this brief, a novel power and speed optimization methodology of current mode logic (CML) dividers is presented, which is based on the injection-locking concept from injection-locked frequency dividers. It helps to realize a CML divider of high performance, including high operation frequency, low power consumption, and a wide division locking range. This concept is newly introduced to explain wh... View full abstract»

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  • CMOS UWB Multiplier

    Publication Year: 2011, Page(s):570 - 574
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB) | HTML iconHTML

    A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 × 700 μm2. The overall power consumpt... View full abstract»

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  • 1.5-V Complex Filters Using Current Mirrors

    Publication Year: 2011, Page(s):575 - 579
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (614 KB) | HTML iconHTML

    The derivation of complex filter topologies according to leapfrog and topological emulation techniques is presented in this brief, where the employed active elements are low-voltage current mirrors. Thus, the offered benefits are the capability of operating in a modern low-voltage environment, the absence of resistors, and the electronic tuning of the frequency characteristics. A 12th-order comple... View full abstract»

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  • A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators

    Publication Year: 2011, Page(s):580 - 584
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB) | HTML iconHTML

    This brief presents a pseudorandom number generator that requires very low resources from the hardware design point of view. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary low-complexity linear feedback shift register. We present a predictability and periodicity analysis of the sequences generated by the proposed architecture to show that the system is... View full abstract»

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  • A Spur-Free MASH DDSM With High-Order Filtered Dither

    Publication Year: 2011, Page(s):585 - 589
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (790 KB) | HTML iconHTML

    A novel dithered multistage noise shaping (MASH) digital delta-sigma modulator (DDSM) that produces a spur-free output spectrum is presented. The order of the least significant bit (LSB) dither shaping can be increased to that of the modulator, without producing spurious tones. Theoretical results prove that the quantization noise is asymptotically white and uncorrelated with the input; this is co... View full abstract»

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  • Perceptron Implementation of Triple-Valued Logic Operations

    Publication Year: 2011, Page(s):590 - 594
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    This brief focuses on the perceptron implementation of triple-valued logic functions (TVLFs). Based on the concept of the multiple-valued DNA-like sequence, the weight-threshold values of TVLFs can be formulated with a perceptron. Particularly, the TVLF perceptron implementation of “xor ” and a half-adder are realized successfully with multithreshold activation functions. View full abstract»

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  • Stabilizing the Average-Current-Mode-Controlled Boost PFC Converter via Washout-Filter-Aided Method

    Publication Year: 2011, Page(s):595 - 599
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    The average-current-mode-controlled boost power-factor-correction (PFC) converter may exhibit instability at the line frequency. This nonlinear phenomenon is undesirable. The time-delay feedback control method may stabilize the boost PFC converter by introducing a digital circuit. The digital circuit is difficult to implement. The second-order filter method can also control the instability, but it... View full abstract»

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  • Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic

    Publication Year: 2011, Page(s):600 - 604
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this brief, two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters. Different from conventional DA techniques, our proposed schemes use coe... View full abstract»

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  • Nonseparable Three-Dimensional IIR Notch Filter Design Using Outer Product Expansion

    Publication Year: 2011, Page(s):605 - 609
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (554 KB) | HTML iconHTML

    This brief emphasizes on the 3-D digital notch filter design problem. A standard form of notch filter design is presented in nonseparable form. A rank reduction technique is conducted to expand the 3-D design problem. The 3-D digital notch problem is initially expanded into the 2-D and 1-D filter design problems. Then, the 2-D problem is expanded again into two 1-D problems by using the singular v... View full abstract»

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  • Digital Wideband Integrators With Matching Phase and Arbitrarily Accurate Magnitude Response

    Publication Year: 2011, Page(s):610 - 614
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB) | HTML iconHTML

    A new class of linear-phase infinite-impulse-response digital wideband integrators based on the numerical integration rules is presented. The proposed class of integrators exactly matches the desired phase response of the continuous-time integrator (after group delay compensation) and can approximate the magnitude response as closely as desired by increasing the number of system zeros, i.e., the o... View full abstract»

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  • 2011 IEEE membership form

    Publication Year: 2011, Page(s):615 - 616
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2011, Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2011, Page(s): C4
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Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org