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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 9 • Date Sept. 2011

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Displaying Results 1 - 25 of 36
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010)

    Publication Year: 2011 , Page(s): 1993 - 1995
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  • Technology Variability From a Design Perspective

    Publication Year: 2011 , Page(s): 1996 - 2009
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2757 KB) |  | HTML iconHTML  

    Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design. View full abstract»

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  • The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM

    Publication Year: 2011 , Page(s): 2010 - 2016
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB) |  | HTML iconHTML  

    Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348 MHz and 0.5 V with a read and write power of 3.33 and 1.97 mW, respectively, per 4.5 KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6 V supply, an access speed of 1.2 GHz is observed. View full abstract»

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  • All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control

    Publication Year: 2011 , Page(s): 2017 - 2025
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1483 KB) |  | HTML iconHTML  

    A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on circuit-level performance to enhance silicon debug and adaptive clock control. The DVM consists of a tunable replica circuit, a time-to-digital converter, and multiplexers to measure circuit delay or frequency changes with less than a 1% measured resolution error while capturing clock-to-data correlations. In validating the DVM with microprocessor maximum clock frequency (FMAX) measurements, an on-die noise injector circuit induces a supply voltage (VCC) droop at a particular cycle in the test program. The FMAX measurement is then repeated for over a thousand iterations while shifting the droop placement to a different cycle per iteration. Silicon measurements demonstrate the DVM capability of tracking the worst case FMAX reduction to within 1% for a wide range of VCC droop profiles. Furthermore, silicon measurements reveal that FMAX is highly sensitive to the placement and magnitude of a high-frequency VCC droop during program execution, thus highlighting the value of the DVM for silicon debug. In addition, the DVM interfaces with an adaptive clock control circuit to dynamically adjust the clock frequency by changing the divide ratio in the phase-locked loop in response to persistent variations, enabling the microprocessor to adapt to the operating environment for maximum efficiency. View full abstract»

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  • Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor

    Publication Year: 2011 , Page(s): 2026 - 2037
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1646 KB) |  | HTML iconHTML  

    This paper proposes a low power unified oxide and negative bias temperature instability (NBTI) degradation sensor designed in 45 nm process node. The cell power consumption is 105 lower than a previously proposed sensor. The unified nature enables efficient reliability monitoring with reduced sensor deployment effort and area overhead. Using the sensor dynamic NBTI management (DNM) has been implemented for the first time. DNM trades the excess “reliability margin” present in the design, due to better than worst case operating conditions, with performance. For the typical case shown in this paper, DNM allows for an average boost of 90 mV in accelerated supply voltage while bringing down the excess NBTI margin of 22.5 mV to 8 mV where the total budget for NBTI was 66 mV. View full abstract»

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  • Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial

    Publication Year: 2011 , Page(s): 2038 - 2050
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1441 KB) |  | HTML iconHTML  

    Architectural and circuit techniques to integrate the RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented. Intended for software-defined and cognitive radio platforms, tunable high-Q filters realized by CMOS switches and linear or MOS capacitors allow the integration of highly reconfigurable transceiver front ends that are robust to in-band and out-of-band blockers. Furthermore, duplexer techniques based on electrical balance concepts are introduced to enable highly integrated and programmable radios for full-duplex applications such as 3/4G transceivers. Several case studies are presented that offer highly linear and low-noise transceiver front ends that satisfy the challenging requirements of cellular standards, yet offer considerably lower cost and size compared to the state-of-the-art transceivers available today. View full abstract»

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  • Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

    Publication Year: 2011 , Page(s): 2051 - 2060
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1601 KB) |  | HTML iconHTML  

    We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter. View full abstract»

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  • A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects

    Publication Year: 2011 , Page(s): 2061 - 2068
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1830 KB) |  | HTML iconHTML  

    A 25 Gb/s laser diode (LD) driver has been developed on the basis of standard 65 nm CMOS technology for optical interconnects. The LD driver consists of a main driver capable of providing an average current of 30 mA and a predriver providing a gain of 20 dB. The main driver uses mutually coupled inductors to adjust the inductive peaking to improve eye patterns under various packaging conditions. The predriver uses CMOS active feedback to achieve a wide bandwidth and high gain, despite its small size and low power consumption. The fabricated circuit achieves data rates of 25 Gb/s, consumes 156 mW (6.3 mW/Gb/s) and occupies an area of 0.011 mm2 . View full abstract»

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  • A Low-Power ECoG/EEG Processing IC With Integrated Multiband Energy Extractor

    Publication Year: 2011 , Page(s): 2069 - 2082
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1531 KB) |  | HTML iconHTML  

    Electrocorticography (ECoG) implants have recently demonstrated promising results towards potential use in brain-computer interfaces (BCIs). Spectral changes in ECoG signals can provide insight on functional mapping of sensorimotor cortex. We present a 6.4 μ W electrocorticography (ECoG)/electroencephalography (EEG) processing integrated circuit (EPIC) with 0.46 μVrms noise floor intended for emerging brain-computer interface (BCI) applications. This chip conditions the signal and simultaneously extracts energy in four fully programmable frequency bands. Functionality is demonstrated by tuning the four bands to important frequency bands used by ECoG/EEG applications: α (8-12 Hz), β (18-26 Hz), low-γ (30-50 Hz), and γ (70-100 Hz). Measured results from in vivo ECoG recording from the primary motor cortex of an awake monkey are presented. View full abstract»

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  • A Multibit Dual-Feedback CT \Delta \Sigma Modulator With Lowpass Signal Transfer Function

    Publication Year: 2011 , Page(s): 2083 - 2095
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2572 KB) |  | HTML iconHTML  

    This paper presents a dual-feedback continuous-time delta-sigma modulator that features a signal transfer function with low sensitivity to coefficient variations. The anti-aliasing of this topology is similar to that of the feedback architecture while using only two feedback paths for modulators of any order. The proposed architecture is a good candidate for low-power applications as it shows relaxed amplifier gain-bandwidth requirements for the first integrator. As a proof of concept, a third-order delta-sigma modulator has been implemented and tested which achieves 76 dB dynamic range over 5 MHz signal bandwidth while consuming 6 mW from a 1.2 V supply. The prototype chip, fabricated in a 130 nm CMOS process, provides 70 dB anti-aliasing with no out-of-band peaking in the signal transfer function. View full abstract»

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  • Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

    Publication Year: 2011 , Page(s): 2096 - 2107
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2320 KB) |  | HTML iconHTML  

    This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain. View full abstract»

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  • Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers

    Publication Year: 2011 , Page(s): 2108 - 2113
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    The gain-bandwidth conflict is one the most important limitations of high gain feedback amplifiers. In this tutorial paper we will discuss in a unified manner the most important approaches aimed to design amplifiers with a constant closed-loop bandwidth. Advantages and drawbacks are evidenced and new potential solutions are also formulated. View full abstract»

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  • Comments on “Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers”

    Publication Year: 2011 , Page(s): 2114 - 2116
    Cited by:  Papers (3)
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    In this comment, the previous work on bandwidth enhancement of finite gain amplifiers using two or more opamps is brought to the attention of the reader. An analogy between finite gain amplifiers using opamps and current feedback operational amplifiers is also presented. View full abstract»

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  • Reply to "Comments on Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers"

    Publication Year: 2011 , Page(s): 2117
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (27 KB) |  | HTML iconHTML  

    This paper discussed the comments on avoiding the gain-bandwidth tradeoff in feedback amplifiers. View full abstract»

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  • On the Excess Noise Factor \Gamma of a FET Driven by a Capacitive Source

    Publication Year: 2011 , Page(s): 2118 - 2126
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    The excess noise factor Γ , also known as Ogawa's noise factor, is frequently used in the literature on optical receivers to calculate the noise and sensitivity of FET front-ends. After revisiting its definition and clarifying its applications and limitations, we derive an analytical expression for Γ in terms of the channel noise factor γ, the gate noise factor δ , and the correlation coefficient c. We explain the difference between Γ and γ and discuss the dependence of Γ on the source (photodetector) capacitance. The latter dependence, which is weaker than previously thought, is verified by circuit simulations. Additional insight is obtained by complementing van der Ziel's noise model with Pospieszalski's noise model. Finally, we use the derived expression for Γ to calculate its value from measured noise data of a 0.18- μm CMOS technology. View full abstract»

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  • A 12b 50 MS/s 21.6 mW 0.18 \mu m CMOS ADC Maximally Sharing Capacitors and Op-Amps

    Publication Year: 2011 , Page(s): 2127 - 2136
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2551 KB) |  | HTML iconHTML  

    A 12b 50 MS/s 0.18 μ m CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18 μ m CMOS process demonstrates the measured differential and integral nonlinearities within 0.53 LSB and 2.09 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 60.6 dB and a maximum spurious-free dynamic range of 69.4 dB at 50 MS/s. The ADC with an active die area of 0.93 mm2 consumes 21.6 mW at 50 MS/s and 1.8 V. View full abstract»

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  • Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input

    Publication Year: 2011 , Page(s): 2137 - 2148
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1730 KB) |  | HTML iconHTML  

    In this two-part paper, a design methodology for bus-splitting digital delta-sigma modulators (DDSMs) is presented. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations and experimental results confirm the theoretical predictions. Part I addresses ditherless MASH DDSMs with constant inputs; Part II focuses on DDSMs with dither and sinusoidal inputs. View full abstract»

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  • A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level \Delta -\Sigma Modulated Coarse Tuning

    Publication Year: 2011 , Page(s): 2149 - 2158
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2139 KB) |  | HTML iconHTML  

    This paper presents a dual-path PLL using a hybrid VCO to perform digital based frequency acquisition and analog based bandwidth control. With the mixed-mode dual-path control, the proposed PLL significantly alleviates noise coupling and area problems in the coarse-tuning path while minimizing open-loop gain variation in the fine-tuning path. In the hybrid VCO design, the nonlinearity issue of the capacitor array is addressed and a 1-bit quantizer (bi-level) Δ-Σ modulator is used to mitigate the problem. A 2 GHz PLL implemented in 0.18 μm CMOS exhibits less than +/- 3.5% bandwidth variation and less than 2 dB in-band noise variation over entire tuning range under nominal condition at room temperature. It also shows that more than 30 dB spur reduction is achieved with the bi-level second-order single-loop Δ-Σ modulator when the worst-case spur performance is compared with a second-order MASH modulator. View full abstract»

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  • A Two-Dimensional Configurable Active Silicon Dendritic Neuron Array

    Publication Year: 2011 , Page(s): 2159 - 2171
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1843 KB) |  | HTML iconHTML  

    This paper presents a 2-D programmable dendritic neuron array consisting of a 3× 32 dendritic compartment array and a 1 × 32 somatic compartment array. Each dendritic compartment contains two types of regenerative nonlinearities: a NMDA synaptic nonlinearity and a dendritic spike nonlinearity. The chip supports the programmability of local synaptic weights and the configuration of dendritic morphology for individual neurons through the address-event representation protocol. Neurons can be stimulated and recorded using the same protocol. A novel local cable circuit between neighboring compartments allows one to construct different dendritic morphologies. This chip provides a hardware platform for studying the network behavior of neurons with active dendrites and for investigating the role of different dendritic morphologies in neuronal computation. Based on experimental results from a chip fabricated in a 4-metal, 2-poly, 0.35 μm CMOS technology, this work shows one instance of how dendritic nonlinearities can contribute to neuronal computation, that is, the dendritic spike mechanism can dynamically reduce the mismatch-induced coefficient of variation of the somatic response amplitude from about 40% to 3.5%, and the response timing jitter by a factor of 2. View full abstract»

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  • Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices

    Publication Year: 2011 , Page(s): 2172 - 2181
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1783 KB) |  | HTML iconHTML  

    We present an original method to implement neuro-inspired supervised learning for a synaptic array based on carbon nanotube devices. The device characteristics required to implement on chip learning within a crossbar of carbon nanotube field effect transistors (CNTFETs) as synaptic arrays were experimentally demonstrated and accurately modeled through a specific electrical compact model. We performed electrical simulations of learning for an array of 24 nanotube memory devices corresponding to a 3 input × 3 output neural layer that revealed successful learning of separable logic functions within very few epochs, even when a realistic variability of nanotube diameter was taken into account. Such a learning approach opens the way to the use of high-density synaptic arrays as generic logic blocks in configurable circuits. View full abstract»

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  • Determining the Range of the Power Consumption in Linear DC Interval Parameter Circuits

    Publication Year: 2011 , Page(s): 2182 - 2188
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    The paper considers the following worst-case steady-state tolerance analysis problem: given a linear dc circuit whose resistors and sources have preset tolerances, determine the range of the electrical power consumed in the circuit. It is shown that the power range sought can be computed as the range of an associated interval linear programming problem. A method for solving the latter problem is suggested whose numerical complexity is not a priori exponential. A numerical example illustrating the new method is provided. View full abstract»

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  • Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

    Publication Year: 2011 , Page(s): 2189 - 2200
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1205 KB) |  | HTML iconHTML  

    While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance (such as on noise margin and delay) in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage. View full abstract»

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  • Carry Chains for Ultra High-Speed SiGe HBT Adders

    Publication Year: 2011 , Page(s): 2201 - 2210
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2296 KB) |  | HTML iconHTML  

    Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85°C . A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras