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IEEE Transactions on Computers

Issue 10 • Oct. 2011

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2011, Page(s): c2
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  • An Extended XQDD Representation for Multiple-Valued Quantum Logic

    Publication Year: 2011, Page(s):1377 - 1389
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1859 KB) | HTML iconHTML

    X-decomposition Quantum Decision Diagram (XQDD) can represent a quantum operation and perform matrix operations. It can be used to verify quantum and reversible circuits even if the reversible circuits have different number of garbage qubits. It is efficient in terms of space and time. In this paper, we extend the original XQDD to multiple-valued quantum logic. The extended XQDD can represent a mu... View full abstract»

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  • Self-Routing Quantum Sparse Crossbar Packet Concentrators

    Publication Year: 2011, Page(s):1390 - 1405
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    Quantum switching networks are derived from conventional switching networks by replacing the classical switches by quantum switches. We give the quantum circuit design and routing of an n × m network, called a quantum concentrator that can direct quantum bit packets in arbitrary quantum states from any of its k inputs to some of its k outputs, where 1 ≤ k ≤ m ≤ n. Our d... View full abstract»

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  • Prefetch-Aware Memory Controllers

    Publication Year: 2011, Page(s):1406 - 1430
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2922 KB) | HTML iconHTML

    Existing DRAM controllers employ rigid, nonadaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetches the same as demand requests, and others always prioritize demands over prefetches. However, none of these rigid policies result in the best performance because they do not take into account the usefulness of prefetches. If prefetches are ... View full abstract»

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  • Optimal Storage Placement for Tree-Structured Networks with Heterogeneous Channel Costs

    Publication Year: 2011, Page(s):1431 - 1444
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (998 KB) | HTML iconHTML

    This work considers data query applications in tree-structured networks, where a given set of source nodes generate (or collect) data and forward the data to some halfway storage nodes for satisfying queries that call for data generated by all source nodes. The goal is to determine an optimal set of storage nodes that minimizes overall communication cost. Prior work toward this problem assumed hom... View full abstract»

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  • An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration

    Publication Year: 2011, Page(s):1445 - 1458
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1518 KB) | HTML iconHTML

    The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a single configuration can take an excessive amount of time due to the need to run a set of benchmarks with realistic workloads. This paper proposes a novel machine-learning model that can quickly and accurately predict the per... View full abstract»

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  • Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

    Publication Year: 2011, Page(s):1459 - 1470
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1676 KB) | HTML iconHTML

    The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal... View full abstract»

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  • Two Efficient Algorithms for Linear Time Suffix Array Construction

    Publication Year: 2011, Page(s):1471 - 1484
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (978 KB) | HTML iconHTML

    We present, in this paper, two efficient algorithms for linear time suffix array construction. These two algorithms achieve their linear time complexities, using the techniques of divide-and-conquer, and recursion. What distinguish the proposed algorithms from other linear time suffix array construction algorithms (SACAs) are the variable-length leftmost S-type (LMS) substrings and the fixed-lengt... View full abstract»

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  • Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

    Publication Year: 2011, Page(s):1485 - 1502
    Cited by:  Papers (93)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3806 KB) | HTML iconHTML

    Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes... View full abstract»

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  • Efficient Encoding/Decoding for Second-Order Spectral-Null Codes by Reducing Random Walks

    Publication Year: 2011, Page(s):1503 - 1510
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1578 KB) | HTML iconHTML

    Second-order spectral-null (2-OSN) codes are, in general, constructed from concatenating any codewords in 2-OSN code. Most 2-OSN codes adopt the Tallini-Bose random walk method in encoding and decoding, which exchanges two adjacent bits each time in a binary vector. In this brief contribution, we give a new implementation of the Tallini-Bose random walk method for 2-OSN codes which is shown by exp... View full abstract»

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  • Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution

    Publication Year: 2011, Page(s):1511 - 1516
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (699 KB) | HTML iconHTML

    A novel concurrent soft error detection and correction scheme is introduced for parallel hardware implementations of transform-based convolution. The proposed technique is based on the structure of radix-2 Fast Fourier Transforms (FFT) of length 2n where n is an integer. The scheme can provide up to 100 percent detection and correction of isolated single soft errors in the convolution a... View full abstract»

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  • Call For Papers: Networks-on-Chip

    Publication Year: 2011, Page(s): 1517
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  • Call For Papers: Energy Efficient Computing

    Publication Year: 2011, Page(s): 1518
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  • Call For Papers: System-Level Design and Validation of Heterogeneous Chip Multiprocessors

    Publication Year: 2011, Page(s): 1519
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  • New Transactions on Computers Essential Sets Available

    Publication Year: 2011, Page(s): 1520
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  • TC Information for authors

    Publication Year: 2011, Page(s): c3
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  • [Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org