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IEE Proceedings E - Computers and Digital Techniques

Issue 4 • Jul 1993

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Displaying Results 1 - 8 of 8
  • Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods

    Publication Year: 1993, Page(s):196 - 199
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (368 KB)

    The paper presents a comparative study of circuit area and performance degradation among four pipelined RISC processors using different precise interrupt methods. The precise interrupt methods studied in the paper include in-order completion, reorder buffer, history file and future file. The VHDL is used to model five machines at the register transfer level. The Synopsys design compiler is used to... View full abstract»

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  • Unidirectional cube connected cycles

    Publication Year: 1993, Page(s):191 - 195
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    Cube connected cycles (CCC), a popular and layout-efficient alternative to the hypercube, uses duplex dimensional links. The paper proposes a variant of the CCC interconnection using simplex dimensional links. Usage of simplex links (instead of duplex) is shown to have design advantages. Cost-performance comparison of the proposed 'directed cube connected cycles' (DCCC) structure with bidirectiona... View full abstract»

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  • Binary-tree timing simulation with consideration of internal charges

    Publication Year: 1993, Page(s):211 - 219
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (544 KB)

    An accurate and efficient block-level timing simulator is described. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the wave-form, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a... View full abstract»

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  • Radix-2n multiplier structures: a structured design methodology

    Publication Year: 1993, Page(s):185 - 190
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (488 KB)

    A new radix-2n multiplication algorithm is presented which is iterative and modular. The algorithm is a true generalisation of the radix-2 (conventional binary) multiplication algorithm. As a result, existing radix-2 (binary) structures can easily be generalised for all radices. The architecture of the basic cell is not fixed for all radices: any architecture can be used if its function... View full abstract»

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  • Hybrid signed digit logarithmic number system processor

    Publication Year: 1993, Page(s):205 - 210
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (412 KB)

    A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. ... View full abstract»

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  • SIMD matrix methods for detecting hazards in logic circuits

    Publication Year: 1993, Page(s):201 - 204
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (224 KB)

    The paper describes the underlying theory and an outline for an algorithm which is designed to utilise the power of SIMD computers to detect and locate the presence of logic hazards in combinational logic circuits. View full abstract»

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  • Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits

    Publication Year: 1993, Page(s):220 - 226
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (480 KB)

    With the recent achievement of lower power and higher densities, bipolar ECL technology is expected to be used widely in high performance digital circuits. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. The paper presents a detailed analysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults betwe... View full abstract»

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  • Datapath synthesis using onchip multiport memories

    Publication Year: 1993, Page(s):227 - 232
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (388 KB)

    Recently there has been a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation and are used in the design of many recent high-speed RISC and superscalar processors. An efficient design methodology for datapath synthesis using onchip multiport memories is presented which ca... View full abstract»

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