Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Computers and Digital Techniques, IEE Proceedings E

Issue 4 • Date Jul 1993

Filter Results

Displaying Results 1 - 8 of 8
  • Hybrid signed digit logarithmic number system processor

    Publication Year: 1993 , Page(s): 205 - 210
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SIMD matrix methods for detecting hazards in logic circuits

    Publication Year: 1993 , Page(s): 201 - 204
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    The paper describes the underlying theory and an outline for an algorithm which is designed to utilise the power of SIMD computers to detect and locate the presence of logic hazards in combinational logic circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Binary-tree timing simulation with consideration of internal charges

    Publication Year: 1993 , Page(s): 211 - 219
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    An accurate and efficient block-level timing simulator is described. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the wave-form, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a consideration of the various fan-out effect and various cell-size effects. Efficient delay calculation is accomplished through a logic-level simulator instead of using a transistor-level simulator. To represent the waveform accurately, the switching delay and slope are defined and calculated with consideration of the internal charges. To consider the internal charges when computing the waveform, a merged PN tree is used to represent a CMOS gate. The characteristics of the PN tree are described and the methods used to evaluate the conducting paths proposed. The relationship between the RC time constant and the slope waveform is investigated. After the conducting paths are obtained, a recursive algorithm can be applied to compute the RC time constant in series-parallel RC networks, followed by switching delay and slope. The results are satisfactory when compared with Spice. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods

    Publication Year: 1993 , Page(s): 196 - 199
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    The paper presents a comparative study of circuit area and performance degradation among four pipelined RISC processors using different precise interrupt methods. The precise interrupt methods studied in the paper include in-order completion, reorder buffer, history file and future file. The VHDL is used to model five machines at the register transfer level. The Synopsys design compiler is used to synthesise these machines as a netlist of CMOS logic gates, then gate counts are obtained. Based on the model architecture and benchmark programs, it shows that the history file method can achieve the highest performance and consume less silicon area than the reorder buffer method and the future file method. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Radix-2n multiplier structures: a structured design methodology

    Publication Year: 1993 , Page(s): 185 - 190
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A new radix-2n multiplication algorithm is presented which is iterative and modular. The algorithm is a true generalisation of the radix-2 (conventional binary) multiplication algorithm. As a result, existing radix-2 (binary) structures can easily be generalised for all radices. The architecture of the basic cell is not fixed for all radices: any architecture can be used if its functionality satisfies the multiply/add principle presented. The multiplier architecture is first defined in terms of the radix-2n multiplication algorithm which is general for all n. This results in an architecture being available for every n. The tradeoff between cost and time is achieved by optimising the basic cell architecture for each radix and choosing the radix that results in the best performance. This approach is applied to the design of serial and serial/parallel multipliers, and an iterative multiplier array. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Datapath synthesis using onchip multiport memories

    Publication Year: 1993 , Page(s): 227 - 232
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    Recently there has been a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation and are used in the design of many recent high-speed RISC and superscalar processors. An efficient design methodology for datapath synthesis using onchip multiport memories is presented which can be applied to scheduled algorithms to reduce the design space. Based on simple and clear, but powerful principles, the proposed technique not only groups variables into a minimum number of multiport memories depending on their ports and access requirements of variables, but also minimises their interconnection hardware (such as buses, multiplexers and tristate buffers) to functional units. The system (memory allocator package) supports the synthesis of architecture in both linear topology and random topology for the application specific designs. The minimisation problems have been formulated as 0-1 integer linear programming problems. Experiments on benchmarks show promising results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unidirectional cube connected cycles

    Publication Year: 1993 , Page(s): 191 - 195
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Cube connected cycles (CCC), a popular and layout-efficient alternative to the hypercube, uses duplex dimensional links. The paper proposes a variant of the CCC interconnection using simplex dimensional links. Usage of simplex links (instead of duplex) is shown to have design advantages. Cost-performance comparison of the proposed 'directed cube connected cycles' (DCCC) structure with bidirectional CCC is shown. DCCC layout is compared with CCC layout and a routing algorithm for DCCC is proposed. A method for porting CCC algorithms to DCCC is provided, and the extent of slowdown is evaluated. DCCC can embed a loop with unit dilation and unit expansion. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits

    Publication Year: 1993 , Page(s): 220 - 226
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    With the recent achievement of lower power and higher densities, bipolar ECL technology is expected to be used widely in high performance digital circuits. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. The paper presents a detailed analysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults between logical units without feedback and logical units with feedback in ECL are presented. An analytical approach is presented for computation of logic levels at ECL outputs under varying unknown bridging resistances. Effects of bridging faults and bridging resistances on output logic levels in ECL have been examined along with their effects on noise immunity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.