IEEE Transactions on Electron Devices

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Publication Year: 2011, Page(s):C1 - 2822
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2011, Page(s): C2
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• Changes in the Editorial Board

Publication Year: 2011, Page(s): 2823
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• Atomistic Investigation of Low-Field Mobility in Graphene Nanoribbons

Publication Year: 2011, Page(s):2824 - 2830
Cited by:  Papers (24)
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We have investigated the main scattering mechanisms affecting the mobility in graphene nanoribbons using detailed atomistic simulations. We have considered carrier scattering due to acoustic and optical phonons, edge roughness, single defects, and ionized impurities, and we have defined a methodology based on simulations of statistically meaningful ensembles of nanoribbon segments. Edge disorder h... View full abstract»

• Interconnect Network Analysis of Many-Core Chips

Publication Year: 2011, Page(s):2831 - 2837
Cited by:  Papers (4)
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This paper presents the first intercore interconnect technology optimization and wiring demand calculation for mesh, concentrated mesh, flattened butterfly, and concentrated flattened butterfly network-on-chip topologies. Global wire dimensions are optimized to achieve maximum bandwidth and minimum delay. The core-to-core channel width is then determined by taking into account the available wiring... View full abstract»

• A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

Publication Year: 2011, Page(s):2838 - 2846
Cited by:  Papers (8)
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The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Qinv and effective mobility μeff has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such ... View full abstract»

• Radio-Frequency Transistors Using Chemical-Vapor-Deposited Monolayer Graphene: Performance, Doping, and Transport Effects

Publication Year: 2011, Page(s):2847 - 2853
Cited by:  Papers (18)
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Large-area graphene is synthesized by Cu-catalyzed chemical vapor deposition (CVD), transistors are constructed, and the dc/RF performance is examined. Top-gate transistors, i.e., with a gate length of 3 μm and Vds = 5 V, have a peak dc transconductance in excess of 20 mS/mm and a drive current of 0.5 A/mm. RF measurements achieve gigahertz extrinsic current-gain cutoff frequency... View full abstract»

• An Inversion-Charge Analytical Model for Square Gate-All-Around MOSFETs

Publication Year: 2011, Page(s):2854 - 2861
Cited by:  Papers (6)
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A new approach to the analytical solution of the 2-D Poisson equation including the inversion-charge density in undoped square gate-all-around metal-oxide-semiconductor field-effect transistors has been developed. We have obtained functions with different degrees of complexity to calculate the electric potential in the devices under study. The results obtained are compared with the data simulated ... View full abstract»

• A Circuit Simulation Method Based on Physical Approach for the Analysis of Mot_bal99lt1 p-i-n Diode Circuits

Publication Year: 2011, Page(s):2862 - 2870
Cited by:  Papers (5)
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To simulate semiconductor devices and circuits working at high frequencies or under a large signal input and to better understand their physical effects, a physically based simulation method is proposed in this paper. It utilizes a physical-model-based field simulation to analyze the semiconductor devices in a circuit and incorporates the field simulation into an equivalent-model-based circuit sim... View full abstract»

• Analytical Correction for Effective Mobility Measurements in MOSFETs

Publication Year: 2011, Page(s):2871 - 2873
Cited by:  Papers (2)
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Differences in drain bias used for the capacitance and current measurement steps can lead to inaccuracy in the extraction of mobility at low fields. An analytical correction for a bulk MOSFET can be applied to the capacitance measurement to correct for the effect of drain bias provided doping and oxide capacitance density are known. The proposed correction successfully corrects measured mobility d... View full abstract»

• Comprehensive Microscopic Analysis of Laser-Induced High Doping Regions in Silicon

Publication Year: 2011, Page(s):2874 - 2877
Cited by:  Papers (10)
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Microscopic laser-doped regions in advanced solar cell concepts are analyzed to determine the doping density and to identify the damage caused by the laser process. For these investigations, microphotoluminescence spectroscopy and micro-Raman spectroscopy are utilized to measure doping density, internal stress, and carrier lifetime with micrometer resolution. This analysis proves the high applicab... View full abstract»

• A Physical Model of the Temperature Dependence of the Current Through $hbox{SiO}_{2}hbox{/}hbox{HfO}_{2}$ Stacks

Publication Year: 2011, Page(s):2878 - 2887
Cited by:  Papers (107)  |  Patents (2)
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In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/HfO2 gate dielectric stacks in a wide temperature range (6 K-400 K). We simulated the temperature dependence of the I -V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunnelin... View full abstract»

• Fourier Transform Infrared Spectroscopy of Moisturized Low- $kappa$ Dielectric Materials

Publication Year: 2011, Page(s):2888 - 2894
Cited by:  Papers (6)
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A dense plasma enhanced chemical vapor deposition (PECVD) SiCOH film and a porous ultralow-κ (pULK) film have been investigated by means of the Fourier transform infrared spectroscopy. Structural differences between both materials have been found in particular in the amount of silanol groups and in the location and shape of the Si-O-Si stretching vibration band. Furthermore, moisturized sam... View full abstract»

• Study of High-Performance Ge pMOSFET Scaling Accounting for Direct Source-to-Drain Tunneling

Publication Year: 2011, Page(s):2895 - 2902
Cited by:  Papers (6)
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Drift-diffusion models are used in conjunction with Monte Carlo simulations to study and compare the scalability of germanium (Ge) versus silicon (Si) p-channel double-gate MOSFETs near the end of the technology roadmap. Direct source-to-drain tunneling (DSDT) and uniaxial compressive stress effects are taken into account. The higher dielectric constant of Ge results in degraded short-channel effe... View full abstract»

• Theory of the Junctionless Nanowire FET

Publication Year: 2011, Page(s):2903 - 2910
Cited by:  Papers (92)
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In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its ne... View full abstract»

• Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

Publication Year: 2011, Page(s):2911 - 2916
Cited by:  Papers (28)
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In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO2, Al2O3, and HfO2, and show a performance enhancement when using high-k dielectric materials. The best performance is achieved for the devices using Hf... View full abstract»

• Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate

Publication Year: 2011, Page(s):2917 - 2923
Cited by:  Papers (2)
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Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) do... View full abstract»

• Nonvolatile Amorphous-Silicon Thin-Film-Transistor Memory Structure for Drain-Voltage Independent Saturation Current

Publication Year: 2011, Page(s):2924 - 2927
Cited by:  Papers (6)
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Transistors with floating gate, used for nonvolatile memory, have a saturation current that increases with drain voltage. This is the result of undesirable capacitive coupling between the floating gate and the drain electrode, which can occur in devices made on crystalline silicon or amorphous silicon (a-Si) technologies. In this paper, we report on a new a-Si thin-film transistor memory structure... View full abstract»

• Impact of AlTaO Dielectric Capping on Device Performance and Reliability for Advanced Metal Gate/High-$k$ PMOS Application

Publication Year: 2011, Page(s):2928 - 2935
Cited by:  Papers (1)
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We have investigated the effect of ultrathin Al-Ta-based capping layers on HfO2 and experimentally demonstrated that, with proper Al and Ta composition, an AlTaO capping layer is a good candidate dielectric for PMOSFET devices. Lower threshold voltage and significantly improved mobility were observed with AlTaO capping without degrading the dielectric properties. The addition of Ta in a... View full abstract»

• TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

Publication Year: 2011, Page(s):2936 - 2943
Cited by:  Papers (33)
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In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-κ), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with... View full abstract»

• Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process

Publication Year: 2011, Page(s):2944 - 2951
Cited by:  Papers (18)
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In high-voltage technologies, silicon-controlled rectifier (SCR) is usually embedded in output arrays to provide a robust and self-protected capability against electrostatic discharge (ESD). Although the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mistriggering of the embedded SCR during normal circuit operating conditions can bring other application reliabi... View full abstract»

• Characterization of the Variable Retention Time in Dynamic Random Access Memory

Publication Year: 2011, Page(s):2952 - 2958
Cited by:  Papers (7)
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To study the relationship between the original leakage current fluctuation and the detected variable retention time (VRT) from the retention test of dynamic random access memory (DRAM), we simulated the real procedure of the VRT measurement of DRAM. By investigating the results of the simulation, we proposed a new effective VRT measurement method based on the comparison between measurement and sim... View full abstract»

• Asymmetric Independent-Gate MOSFET SRAM for High Stability

Publication Year: 2011, Page(s):2959 - 2965
Cited by:  Papers (7)
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In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array ... View full abstract»

• 3-D Vertical FG nand Flash Memory With a Novel Electrical S/D Technique Using the Extended Sidewall Control Gate

Publication Year: 2011, Page(s):2966 - 2973
Cited by:  Papers (3)
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We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure... View full abstract»

• Development of a New pHEMT-Based Electrostatic Discharge Protection Structure

Publication Year: 2011, Page(s):2974 - 2980
Cited by:  Papers (6)  |  Patents (2)
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Electrostatic discharge (ESD) protection structures in the GaAs technology are commonly constructed using enhancement-mode single-gate (SG) pseudomorphic high-electron mobility transistor (pHEMT) devices. This paper develops an improved ESD protection clamp based on a novel multigate pHEMT. With approximately the same layout area, the proposed ESD protection clamp can carry an ESD current three ti... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy