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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 9 • Sept. 2011

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  • Table of contents

    Publication Year: 2011, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2011, Page(s): C2
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  • Automated Range and Precision Bit-Width Allocation for Iterative Computations

    Publication Year: 2011, Page(s):1265 - 1278
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (535 KB) | HTML iconHTML

    As scientific computing becomes more widespread in environments where form-factor considerations necessitate hardware acceleration, the problem of selecting numerical data representations (bit-width allocation), key to accelerator design, is faced with shortcomings in the existing techniques. To address this problem for scientific computing dataflows, we propose a methodology for determining custo... View full abstract»

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  • Transforming Probabilities With Combinational Logic

    Publication Year: 2011, Page(s):1279 - 1292
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (470 KB) | HTML iconHTML

    Schemes for probabilistic computation can exploit physical sources to generate random values in the form of bit streams. Generally, each source has a fixed bias and so provides bits with a specific probability of being one. If many different probability values are required, it can be expensive to generate all of these directly from physical sources. This paper demonstrates novel techniques for syn... View full abstract»

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  • Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling

    Publication Year: 2011, Page(s):1293 - 1306
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1277 KB) | HTML iconHTML

    Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3-D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware th... View full abstract»

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  • QLMOR: A Projection-Based Nonlinear Model Order Reduction Approach Using Quadratic-Linear Representation of Nonlinear Systems

    Publication Year: 2011, Page(s):1307 - 1320
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB) | HTML iconHTML

    We present a projection-based nonlinear model order reduction method, named model order reduction via quadratic-linear systems (QLMOR). QLMOR employs two novel ideas: 1) we show that nonlinear ordinary differential equations, and more generally differential-algebraic equations (DAEs) with many commonly encountered nonlinear kernels can be rewritten equivalently in a special representation, quadrat... View full abstract»

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  • Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis

    Publication Year: 2011, Page(s):1321 - 1334
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (811 KB) | HTML iconHTML

    Gate oxide breakdown (OBD) is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip OBD reliability analysis assumes a uniform oxide thickness and worst-case temperature for all devices. In practice, however, gate oxide thickness varies from die-to-die and within-die and hence may cause different reliability for different devices... View full abstract»

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  • Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization

    Publication Year: 2011, Page(s):1335 - 1348
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1046 KB) | HTML iconHTML

    For modern designs, delay optimization significantly facilitates success in design closure owing to its more realistic metric than wirelength in routing. Obstacle-avoiding rectilinear Steiner tree (OARST) construction is an essential routing problem. With the trends toward Internet protocol-block-based system-on-chip designs, OARST with buffer insertion has been surveyed to diminish the delay of l... View full abstract»

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  • Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems

    Publication Year: 2011, Page(s):1349 - 1358
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB) | HTML iconHTML

    In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in ... View full abstract»

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  • Temperature Aware Dynamic Workload Scheduling in Multisocket CPU Servers

    Publication Year: 2011, Page(s):1359 - 1372
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (746 KB) | HTML iconHTML

    In this paper, we propose a multitier approach for significantly lowering the cooling costs associated with fan subsystems without compromising the system performance. Our technique manages the fan speed by intelligently allocating the workload at the core level as well as at the CPU socket level. At the core level we propose a proactive dynamic thermal management scheme. We introduce a new predic... View full abstract»

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  • An Optimal and Practical Approach to Single Constant Multiplication

    Publication Year: 2011, Page(s):1373 - 1386
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB) | HTML iconHTML

    We propose an exact solution to the single constant multiplication (SCM) problem. Existing optimal algorithms are limited to constants of up to 19 bits. Our algorithm requires less than 10 s on average to find a solution for a 32 bit constant. Optimality is guaranteed via an exhaustive search. We analyze two common SCM frameworks and the corresponding search strategies that each framework facilita... View full abstract»

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  • Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

    Publication Year: 2011, Page(s):1387 - 1399
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB) | HTML iconHTML

    The energy usage of on-chip interconnects is a concern for many system-on-chips targeting portable battery-powered devices. We have designed and evaluated a network-on-chip (NoC) for such an application, including tools to optimize for power and communication latency. Our asynchronous (clockless) network operates with efficient two-phase bundled-data links and four-phase routers. The topology and ... View full abstract»

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  • Estimation of Analog Parametric Test Metrics Using Copulas

    Publication Year: 2011, Page(s):1400 - 1410
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB) | HTML iconHTML

    A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their margi... View full abstract»

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  • Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

    Publication Year: 2011, Page(s):1411 - 1415
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (601 KB) | HTML iconHTML

    ATPG based on Boolean satisfiability (SAT) turned out to be a robust alternative to classical structural automatic test pattern generation (ATPG) algorithms performing very well especially for hard-to-detect faults but suffer from the overhead for easy-to-detect faults. In this letter, we propose new efficient data structures and methodologies for SAT-based ATPG. The novel incremental SAT solving ... View full abstract»

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  • Scan Shift Power of Functional Broadside Tests

    Publication Year: 2011, Page(s):1416 - 1420
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (99 KB) | HTML iconHTML

    The power dissipation during the application of scan-based tests can be significantly higher than during functional operation. An exception is the second, fast functional capture cycles of functional broadside tests, where it is guaranteed that the power dissipation will not exceed that possible during functional operation. The power dissipation during the other clock cycles of functional broadsid... View full abstract»

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  • A Multi-Site Test Solution for Quadrature Modulation RF Transceivers

    Publication Year: 2011, Page(s):1421 - 1425
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    In this letter, we present a 2x-site test solution for radio frequency transceivers using only baseband signals for analysis. We perform all operations on communication standard-compliant signal packets, thereby putting the device under the normal operating conditions. The transmitter on one device under test (DUT) is coupled with a receiver on another DUT to form a complete transmitter-to-receive... View full abstract»

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    Publication Year: 2011, Page(s): 1426
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  • IEEE copyright form

    Publication Year: 2011, Page(s):1427 - 1428
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2011, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2011, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu