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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2011, Page(s):C1 - C4
| PDF (40 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2011, Page(s): C2
| PDF (39 KB)
• ### Digitally Assisted Feedforward Compensation of Cartesian-Feedback Power-Amplifier Systems

Publication Year: 2011, Page(s):457 - 461
Cited by:  Papers (8)
| | PDF (577 KB) | HTML

This brief describes digitally assisted feedforward compensation to extend the bandwidth and to enhance the in-band linearity of Cartesian-feedback (CFB) power-amplifier (PA) systems. The proposed technique combines the strength of the CFB, which is chiefly relaxed PA modeling requirements, with the increased speed of digital predistortion (DPD). CFB is used initially to train efficiently a lookup... View full abstract»

• ### An Active Inductor-Based VCO With Wide Tuning Range and High DC-to-RF Power Efficiency

Publication Year: 2011, Page(s):462 - 466
Cited by:  Papers (16)
| | PDF (385 KB) | HTML

An active inductor-based voltage-controlled oscillator (VCO) with a wide frequency tuning range was designed and fabricated using a standard 0.13-μm CMOS process. The oscillator has an LC-tank topology with cross-coupled transistors, and the active inductor was realized using a pair of fully differential very high-speed operational transconductance amplifiers. Due to the differential... View full abstract»

• ### LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology

Publication Year: 2011, Page(s):467 - 471
Cited by:  Papers (5)
| | PDF (314 KB) | HTML

In this brief, a conventional LC voltage-controlled oscillator (LC-VCO) for Global System for Mobile Communications 900 applications is implemented in a 32-nm CMOS technology. The transition to 32-nm technology represents a big step from the technological point of view, mainly due to the introduction of high-κ dielectrics. In spite of the considered ultrascaled technology, the measur... View full abstract»

• ### A 2.4-GHz Extended-Range Type-I $SigmaDelta$ Fractional-$N$ Synthesizer With 1.8-MHz Loop Bandwidth and $-$110-dBc/Hz Phase Noise

Publication Year: 2011, Page(s):472 - 476
Cited by:  Papers (11)  |  Patents (1)
| | PDF (614 KB) | HTML

Low-power low-loop-bandwidth (BW) integer-N frequency synthesizers with low phase noise have been reported previously. However, achieving similar power/phase-noise performance for a fractional-N synthesizer with a wide loop BW along with excellent spur performance has been challenging. A conventional fractional-N synthesizer is clocked by a crystal oscillator operating at a reference frequency (f<... View full abstract»

• ### A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications

Publication Year: 2011, Page(s):477 - 481
Cited by:  Papers (3)
| | PDF (599 KB) | HTML

This brief presents an all-digital synchronous clock generator with an open-loop architecture, which achieves a fast lock and a wide range for mobile applications. The proposed architecture based on a clock-synchronized delay adopts a multipath delay line, which provides a high resolution and a low deterministic jitter with calibration circuits. A frequency range selector with a locking range movi... View full abstract»

• ### Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network

Publication Year: 2011, Page(s):482 - 486
Cited by:  Papers (6)
| | PDF (795 KB) | HTML

This brief presents an electrostatic discharge (ESD)-protected receiver front-end for wireless communications around 24 GHz. A Π-type input matching network incorporating two split ESD capacitances and an on-chip inductor is constructed to realize the source impedance transformation for high gain, good input matching, and only slightly degraded noise figure (NF). The measured results show t... View full abstract»

• ### A 1–16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector

Publication Year: 2011, Page(s):487 - 491
Cited by:  Papers (10)
| | PDF (495 KB) | HTML

A 1-16-Gb/s wide-range clock and data recovery (CDR) circuit is presented by using the proposed bidirectional frequency detector. This CDR circuit is fabricated in 0.13-μm CMOS technology, and its active area is 0.134 mm2 without a loop filter. The power consumption of this CDR circuit is 160 mW for a supply of 1.5 V. A modified interpolation voltage-controlled oscillator is pres... View full abstract»

• ### A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

Publication Year: 2011, Page(s):492 - 496
Cited by:  Papers (3)
| | PDF (763 KB) | HTML

This brief presents a 6-GHz built-in jitter measurement (BIJM) with the time amplifier (TA) and the multiphase sampler (MPS) to achieve a 1-ps timing resolution. The proposed MPS can reduce the area, and the TA can extend the total timing resolution of BIJM. The self-referenced circuit with the autocalibration technique can eliminate the process variations and create a reference clock being a samp... View full abstract»

Publication Year: 2011, Page(s):497 - 501
Cited by:  Patents (1)
| | PDF (631 KB) | HTML

This brief presents techniques to reduce the blind period of a sampler in high-speed serial link receivers. The impact of the blind period on receiver performance is first investigated. A conventional current-mode logic (CML) master/slave latch-based sampler is reviewed and simulated, followed by the theoretical analysis of the root causes of the sampler blind period. Finally, a proposed sampler i... View full abstract»

• ### A Switching Sequence for Linear Gradient Error Compensation in the DAC Design

Publication Year: 2011, Page(s):502 - 506
Cited by:  Papers (13)  |  Patents (1)
| | PDF (798 KB) | HTML

A switching sequence is proposed to compensate for the linear gradient error in the current source array of current-steering digital-to-analog converter (DAC). A systematic method is established to obtain a switching sequence for both 1-D and 2-D current source arrays. The proposed switching sequence is also validated by the mathematical induction and exhibits a minimum variance of error. The prop... View full abstract»

• ### Finite Common-Mode Rejection in Fully Differential Nonlinear Circuits

Publication Year: 2011, Page(s):507 - 511
Cited by:  Papers (1)
| | PDF (432 KB) | HTML

In this brief, it is highlighted that fully differential nonlinear circuits, even though perfectly symmetrical, can be significantly sensitive to common-mode (CM)/power-supply (PS) interference and can be affected by even-order distortion. The cross-modulation mechanism between CM and differential input components, which gives rise to such unwanted phenomena, is investigated both analytically and ... View full abstract»

• ### Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters

Publication Year: 2011, Page(s):512 - 516
Cited by:  Papers (16)
| | PDF (224 KB) | HTML

In this brief, an efficient technique for implementation of soft-error-tolerant finite impulse response (FIR) filters is presented. The proposed technique uses two implementations of the basic filter with different structures operating in parallel. A soft error occurring in either filter causes the outputs of the filters to differ, or mismatch, for at least one sample. The filters are specifically... View full abstract»

• ### Fast Multiple Inverse Transforms With Low-Cost Hardware Sharing Design for Multistandard Video Decoding

Publication Year: 2011, Page(s):517 - 521
Cited by:  Papers (8)
| | PDF (282 KB) | HTML

In this brief, fast multiple inverse transform algorithms and their hardware sharing designs for 2 × 2, 4 × 4, and 8 × 8 inverse transforms in H.264/Advanced Video Coding and the 8 × 8 inverse transform in Audio Video Coding Standard, 4 × 4 and 8 × 8 inverse transforms in VC-1, and inverse discrete cosine transform in JPEG and MPEG-1/2/4 are developed with... View full abstract»

• ### Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization

Publication Year: 2011, Page(s):522 - 526
Cited by:  Papers (18)  |  Patents (1)
| | PDF (153 KB) | HTML

To achieve a high-throughput decoder, massive-parallel computations are normally applied to the Chien search, but the parallel realization increases the hardware complexity significantly. To reduce the hardware complexity of the parallel Chien search, this brief proposes a 2-D optimization method. In contrast to the previous 1-D optimizations, the proposed method maximizes the sharing of common su... View full abstract»

• ### Cascading Failure Tolerance of Modular Small-World Networks

Publication Year: 2011, Page(s):527 - 531
Cited by:  Papers (25)
| | PDF (454 KB) | HTML

Many real-world networks have a modular structure, and their component may undergo random errors and/or intentional attacks. More devastating situations may happen if the network components have a limited load capacity; the errors and attacks may lead to a cascading component removal process, and consequently, the network may lose its desired performance. In this brief, we investigate the toleranc... View full abstract»

• ### Rader–Brenner Algorithm for Computing New Mersenne Number Transform

Publication Year: 2011, Page(s):532 - 536
Cited by:  Papers (1)
| | PDF (165 KB) | HTML

Error-free convolutions and correlations can be efficiently computed using number theoretic transforms. One particular transform, which is known as the new Mersenne number transform (NMNT), can be used for the calculation of long-length convolutions/correlations. In this brief, a new decimation-in-time algorithm for the fast calculation of the NMNT based on the Rader-Brenner approach is proposed. ... View full abstract»

• ### Robust Quasi-Newton Adaptive Filtering Algorithms

Publication Year: 2011, Page(s):537 - 541
Cited by:  Papers (9)
| | PDF (268 KB) | HTML

Two robust quasi-Newton (QN) adaptive filtering algorithms that perform well in impulsive-noise environments are proposed. The new algorithms use an improved estimate of the inverse of the autocorrelation matrix and an improved weight-vector update equation, which lead to improved speed of convergence and steady-state misalignment relative to those achieved in the known QN algorithms. A stability ... View full abstract»

• ### Special issue on circuits systems and algorithms for compressive sensing

Publication Year: 2011, Page(s): 542
| PDF (101 KB)

Publication Year: 2011, Page(s): 543
| PDF (225 KB)
• ### IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

Publication Year: 2011, Page(s): 544
| PDF (41 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2011, Page(s): C3
| PDF (33 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org