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# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 88
• ### [Front cover]

Publication Year: 2011, Page(s): C1
| PDF (124 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2011, Page(s): C2
| PDF (52 KB)

Publication Year: 2011, Page(s):2185 - 2189
| PDF (85 KB)
• ### Foreword Special Issue on Characterization of Nano CMOS Variability by Simulation and Measurements

Publication Year: 2011, Page(s):2190 - 2196
Cited by:  Papers (1)
| PDF (317 KB) | HTML
• ### Process Technology Variation

Publication Year: 2011, Page(s):2197 - 2208
Cited by:  Papers (139)  |  Patents (8)
| | PDF (2187 KB) | HTML

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variat... View full abstract»

• ### Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors

Publication Year: 2011, Page(s):2209 - 2217
Cited by:  Papers (45)
| | PDF (1001 KB) | HTML

In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space repre sentations are used. Two different cross sections (i.e., 2.2 × 2.2 and 4.2 × 4.... View full abstract»

• ### Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Publication Year: 2011, Page(s):2218 - 2226
Cited by:  Papers (9)
| | PDF (315 KB) | HTML

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in th... View full abstract»

• ### Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results

Publication Year: 2011, Page(s):2227 - 2234
Cited by:  Papers (7)
| | PDF (981 KB) | HTML

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in th... View full abstract»

• ### Characterization and Modeling of Transistor Variability in Advanced CMOS Technologies

Publication Year: 2011, Page(s):2235 - 2248
Cited by:  Papers (12)  |  Patents (1)
| | PDF (1508 KB) | HTML

This paper aims at reviewing the results that we have obtained during the last ten years in the characterization and modeling of transistor mismatch in advanced complementary metal-oxide-semiconductor (CMOS) technologies. First, we review the theoretical background and modeling approaches that are generally employed for analyzing and interpreting the mismatch results. Next, we present the experime... View full abstract»

• ### Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

Publication Year: 2011, Page(s):2249 - 2256
Cited by:  Papers (41)  |  Patents (1)
| | PDF (1706 KB) | HTML

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage V View full abstract»

• ### Statistical Enhancement of the Evaluation of Combined RDD- and LER-Induced $V_{T}$ Variability: Lessons From $hbox{10}^{5}$ Sample Simulations

Publication Year: 2011, Page(s):2257 - 2265
Cited by:  Papers (6)  |  Patents (1)
| | PDF (936 KB) | HTML

Using full-scale 3-D simulations of 100 000s of devices, enabled by “push-button” cluster technology, we study in detail statistical threshold voltage variability in a state-of-the-art n-channel MOSFET introduced by the combined effect of random discrete dopants (RDDs) and line edge roughness (LER) and demonstrate that the resulting distribution is non-normal. Based on careful statis... View full abstract»

• ### An Approach Based on Sensitivity Analysis for the Evaluation of Process Variability in Nanoscale MOSFETs

Publication Year: 2011, Page(s):2266 - 2273
Cited by:  Papers (5)
| | PDF (912 KB) | HTML

We propose an approach to evaluate the effect on the threshold-voltage dispersion of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs) of line-edge roughness, surface roughness, and random dopant distribution. The methodology is fully based on parameter sensitivity analysis, performed by means of a limited number of technology computer-aided design simulations or analytical mo... View full abstract»

• ### A Comparative Study of Surface-Roughness-Induced Variability in Silicon Nanowire and Double-Gate FETs

Publication Year: 2011, Page(s):2274 - 2281
Cited by:  Papers (15)
| | PDF (730 KB) | HTML

We study the effect of surface roughness (SR) at the Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-sp... View full abstract»

• ### Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design

Publication Year: 2011, Page(s):2282 - 2292
Cited by:  Papers (7)
| | PDF (1240 KB) | HTML

This paper identifies and investigates a new source of random threshold voltage variation, which is referred to as Grain-Orientation-induced Quantum Confinement (GOQC) in emerging ultra-thin-body metal-gate complementary metal-oxide-semiconductor (CMOS) devices including FinFET, tri-gate, and nanowire field-effect transistors. Due to the dependence of the work function of the metal gates on their ... View full abstract»

• ### Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

Publication Year: 2011, Page(s):2293 - 2301
Cited by:  Papers (74)
| | PDF (988 KB) | HTML

This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG M... View full abstract»

• ### Compact Modeling of Variability Effects in Nanoscale nand Flash Memories

Publication Year: 2011, Page(s):2302 - 2309
Cited by:  Papers (6)
| | PDF (435 KB) | HTML

This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of... View full abstract»

• ### Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors

Publication Year: 2011, Page(s):2310 - 2316
Cited by:  Papers (24)
| | PDF (553 KB) | HTML

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal-oxide-semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices.... View full abstract»

• ### Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

Publication Year: 2011, Page(s):2317 - 2325
Cited by:  Papers (27)
| | PDF (1417 KB) | HTML

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension reg... View full abstract»

• ### On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Publication Year: 2011, Page(s):2326 - 2336
Cited by:  Papers (31)  |  Patents (1)
| | PDF (1116 KB) | HTML

In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability σ(V)T lower than A(V)T = ... View full abstract»

• ### A Three-Dimensional Physical Model for $V_{rm th}$ Variations Considering the Combined Effect of NBTI and RDF

Publication Year: 2011, Page(s):2337 - 2346
Cited by:  Papers (7)  |  Patents (1)
| | PDF (1469 KB) | HTML

Aggressive transistor scaling affects the threshold voltage Vth in two ways: space and time. Transistors on the same die can have different Vth due to random dopant fluctuations (RDFs). On the other hand, Vth of a specific transistor can randomly shift in time due to random position of dangling bonds and random motion of atomic H or H2 View full abstract»

• ### Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

Publication Year: 2011, Page(s):2347 - 2353
Cited by:  Papers (21)
| | PDF (462 KB) | HTML

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randoml... View full abstract»

• ### Reduction of Fixed-Position Noise in Position-Sensitive Single-Photon Avalanche Diodes

Publication Year: 2011, Page(s):2354 - 2361
Cited by:  Papers (9)
| | PDF (979 KB) | HTML

By ignoring events originating in noisy areas of a position-sensitive single-photon avalanche diode (SPAD), reduction of noise from fixed-position defects is experimentally shown. Additional experimental results from a position-sensitive SPAD integrated in a high-voltage 0.35-μm technology are presented. An effect reducing the active area is described, quantified, and experimentally measure... View full abstract»

• ### Impact of Ge Content and Recess Depth on the Leakage Current in Strained $hbox{Si}_{1-x}hbox{Ge}_{x}/hbox{Si}$ Heterojunctions

Publication Year: 2011, Page(s):2362 - 2370
Cited by:  Papers (1)
| | PDF (608 KB) | HTML

A study of the impact of the Ge content and the recess depth on the leakage current of strained Si1-xGex/Si p+n heterojunctions is presented. A rise in the current, when the Ge content increases and/or the recess depth decreases, is experimentally observed. An analysis of the physical variables involved in the leakage current at low electric fields is carried ou... View full abstract»

• ### Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates

Publication Year: 2011, Page(s):2371 - 2377
Cited by:  Papers (21)  |  Patents (22)
| | PDF (775 KB) | HTML

A new concept of multibody single-transistor dynamic-random-access-memory cell fully compatible with both standard bulk and silicon-on-insulator substrates is presented. Its novelty comes from the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction), which define a body partitioning for hole storage and current sense. The charge accumulated in the top body contr... View full abstract»

• ### Performance Assessment of Nanoscale Field-Effect Diodes

Publication Year: 2011, Page(s):2378 - 2384
Cited by:  Papers (8)  |  Patents (2)
| | PDF (842 KB) | HTML

We propose a new structure called a side-contacted field-effect diode (FED). The fabrication of this new structure is simple, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs is presented. The effect of heavy-doping-induced band-gap narrowing on the performance of FEDs is investigated. Our results show that the calculated Ion/I View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy