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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug. 2011

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Displaying Results 1 - 25 of 88
  • [Front cover]

    Page(s): C1
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Table of contents

    Page(s): 2185 - 2189
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  • Foreword Special Issue on Characterization of Nano CMOS Variability by Simulation and Measurements

    Page(s): 2190 - 2196
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  • Process Technology Variation

    Page(s): 2197 - 2208
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2187 KB) |  | HTML iconHTML  

    Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature. View full abstract»

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  • Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors

    Page(s): 2209 - 2217
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    In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space repre sentations are used. Two different cross sections (i.e., 2.2 × 2.2 and 4.2 × 4.2 nm2) and two different channel lengths (i.e., 6 and 12 nm) have been considered. The resistivity associated with discrete dopants can be estimated from the averaged current-voltage characteristics. The threshold-voltage variability and the sub threshold-slope variability are reduced greatly in the transistors with longer channel length. Both are smaller at equivalent channel lengths in the 2.2 × 2.2 nm2 device due to better electrostatic integrity. At the same time, the ON-state-current variability associated with the varying resistance of the access regions is virtually independent of the channel length. However, it is reduced greatly in the 4.2 × 4.2 nm2 transistor due to a fourfold increase in the number of dopants in the access regions and corresponding self-averaging effects. Finally, we present results for the smallest transistor combining two sources of variability (i.e., discrete random dopants and surface roughness) and phonon scattering. View full abstract»

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  • Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

    Page(s): 2218 - 2226
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology. View full abstract»

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  • Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results

    Page(s): 2227 - 2234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (981 KB) |  | HTML iconHTML  

    Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. Five Fraunhofer institutes joined forces to address these issues. Their own software tools, e.g., for lithography/topography simulation, mixed-mode device simulation, compact model extraction, and behavioral modeling, have been combined with commercial tools to establish a hierarchical system of simulators in order to analyze process variations from their source, e.g., in a lithography step, through device fabrication up to the circuit and system levels. View full abstract»

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  • Characterization and Modeling of Transistor Variability in Advanced CMOS Technologies

    Page(s): 2235 - 2248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1508 KB) |  | HTML iconHTML  

    This paper aims at reviewing the results that we have obtained during the last ten years in the characterization and modeling of transistor mismatch in advanced complementary metal-oxide-semiconductor (CMOS) technologies. First, we review the theoretical background and modeling approaches that are generally employed for analyzing and interpreting the mismatch results. Next, we present the experimental procedures and methodologies that we used for characterizing the transistor matching. Then, we discuss typical matching results that were obtained on modern CMOS technologies and analyze the main variability (mismatch) sources. Finally, we conclude by summarizing our findings and giving some recommendations for future technologies. View full abstract»

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  • Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

    Page(s): 2249 - 2256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1706 KB) |  | HTML iconHTML  

    Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage Vdd dependence of the static noise margin (SNM), and this scattered Vdd dependence of the SNM is not explained by the measured threshold voltage Vth variability alone, indicating that the circuit simulation taking only the Vth variability into account will not predict the SRAM stability precisely at low supply voltage. View full abstract»

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  • Statistical Enhancement of the Evaluation of Combined RDD- and LER-Induced V_{T} Variability: Lessons From \hbox {10}^{5} Sample Simulations

    Page(s): 2257 - 2265
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    Using full-scale 3-D simulations of 100 000s of devices, enabled by “push-button” cluster technology, we study in detail statistical threshold voltage variability in a state-of-the-art n-channel MOSFET introduced by the combined effect of random discrete dopants (RDDs) and line edge roughness (LER) and demonstrate that the resulting distribution is non-normal. Based on careful statistical analysis of the results, we show how the resulting distribution of VT can be constructed from the distributions arising from the individual simulation of RDD and LER variability. In accomplishing this task, we have deployed computationally efficient statistical enhancement techniques that drastically reduce the computational effort needed to accurately characterize threshold voltage variability under the combined influence of RDD and LER. View full abstract»

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  • An Approach Based on Sensitivity Analysis for the Evaluation of Process Variability in Nanoscale MOSFETs

    Page(s): 2266 - 2273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB) |  | HTML iconHTML  

    We propose an approach to evaluate the effect on the threshold-voltage dispersion of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs) of line-edge roughness, surface roughness, and random dopant distribution. The methodology is fully based on parameter sensitivity analysis, performed by means of a limited number of technology computer-aided design simulations or analytical modeling. We apply it to different nanoscale transistor structures, i.e., bulk 45-nm n-channel, 32-nm ultrathin-body silicon-on-insulator, and 22-nm double-gate MOSFETs. In all cases, our approach is capable of reproducing with very good accuracy the results obtained through 3-D atomistic statistical simulations at a small computational cost. We believe that the proposed approach can be a powerful tool to understand the role of the main variability sources and to explore the device design parameter space. View full abstract»

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  • A Comparative Study of Surface-Roughness-Induced Variability in Silicon Nanowire and Double-Gate FETs

    Page(s): 2274 - 2281
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    We study the effect of surface roughness (SR) at the Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. View full abstract»

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  • Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design

    Page(s): 2282 - 2292
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    This paper identifies and investigates a new source of random threshold voltage variation, which is referred to as Grain-Orientation-induced Quantum Confinement (GOQC) in emerging ultra-thin-body metal-gate complementary metal-oxide-semiconductor (CMOS) devices including FinFET, tri-gate, and nanowire field-effect transistors. Due to the dependence of the work function of the metal gates on their grain orientations, different parts of the gate in multigate CMOS devices can have different work functions, resulting in a high electric field in the channel (body) of these devices and, hence, in electrical confinement of the carriers. GOQC effect is shown to be the dominant source of the quantum threshold voltage variation in all emerging ultra-thin multi-gate devices including FinFETs. It is also highlighted for the first time that such variations can have significant implications for the performance and reliability of minimum-sized digital circuits such as static random-access memory cells. View full abstract»

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  • Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

    Page(s): 2293 - 2301
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (988 KB) |  | HTML iconHTML  

    This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled. View full abstract»

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  • Compact Modeling of Variability Effects in Nanoscale nand Flash Memories

    Page(s): 2302 - 2309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design. View full abstract»

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  • Low-Frequency Noise Investigation and Noise Variability Analysis in High- k /Metal Gate 32-nm CMOS Transistors

    Page(s): 2310 - 2316
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    Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal-oxide-semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology. View full abstract»

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  • Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

    Page(s): 2317 - 2325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1417 KB) |  | HTML iconHTML  

    The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation. View full abstract»

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  • On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

    Page(s): 2326 - 2336
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB) |  | HTML iconHTML  

    In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability σ(V)T lower than A(V)T = 1.4 mV · μm is demonstrated. We investigated how this good VT variability is reported on the SNM fluctuations σSNM at the SRAM circuit level. It is found experimentally that σSNM is correlated directly to the σ(V)T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The VT variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)T in drive nMOSFETs is the key parameter to control for minimizing σSNM. View full abstract»

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  • A Three-Dimensional Physical Model for V_{\rm th} Variations Considering the Combined Effect of NBTI and RDF

    Page(s): 2337 - 2346
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1469 KB) |  | HTML iconHTML  

    Aggressive transistor scaling affects the threshold voltage Vth in two ways: space and time. Transistors on the same die can have different Vth due to random dopant fluctuations (RDFs). On the other hand, Vth of a specific transistor can randomly shift in time due to random position of dangling bonds and random motion of atomic H or H2 molecules in the oxide [negative bias temperature instability (NBTI)]. These two random effects are not totally independent because the dissociation rate of Si-H bonds at the silicon-oxide interface depends on the nonuniform electric field. In this paper, we describe the combined effect of RDF and NBTI on Vth using stochastic differential equation. In this paper, we are able to examine the effect of RDF on critical NBTI parameters such as kf, kr, and temperature and the correlation among these parameters. The efficacy of the proposed model is evaluated by performing Monte Carlo simulations on various transistors under different direct-current stress and obtained distributions for NIT and Vth. View full abstract»

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  • Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

    Page(s): 2347 - 2353
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    This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes. View full abstract»

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  • Reduction of Fixed-Position Noise in Position-Sensitive Single-Photon Avalanche Diodes

    Page(s): 2354 - 2361
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    By ignoring events originating in noisy areas of a position-sensitive single-photon avalanche diode (SPAD), reduction of noise from fixed-position defects is experimentally shown. Additional experimental results from a position-sensitive SPAD integrated in a high-voltage 0.35-μm technology are presented. An effect reducing the active area is described, quantified, and experimentally measured using multiple techniques, with an observed inactive distance of roughly 2 μm near the guard rings. The standard characterization results for multiple SPAD geometries are presented, along with the results of noise reduction in a single high-noise SPAD. Characterization results show a photon detection probability above 35%, a dark count rate density in the tens of Hz/μm2, and a signal-to-noise ratio increase of 8 dB for a noisy diode in low light. View full abstract»

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  • Impact of Ge Content and Recess Depth on the Leakage Current in Strained \hbox {Si}_{1-x}\hbox {Ge}_{x}/\hbox {Si} Heterojunctions

    Page(s): 2362 - 2370
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    A study of the impact of the Ge content and the recess depth on the leakage current of strained Si1-xGex/Si p+n heterojunctions is presented. A rise in the current, when the Ge content increases and/or the recess depth decreases, is experimentally observed. An analysis of the physical variables involved in the leakage current at low electric fields is carried out. The Shockley-Read-Hall lifetime is identified as the variable that affects the leakage current the most. Changes in the lifetimes are correlated to changes in the Ge content and the recess depth (Si1-xGex thickness) by means of modifications of the stress levels. An expression that directly relates the values of the lifetimes with the germanium content is proposed. View full abstract»

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  • Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates

    Page(s): 2371 - 2377
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (775 KB) |  | HTML iconHTML  

    A new concept of multibody single-transistor dynamic-random-access-memory cell fully compatible with both standard bulk and silicon-on-insulator substrates is presented. Its novelty comes from the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction), which define a body partitioning for hole storage and current sense. The charge accumulated in the top body controls the current flowing through the bottom body. The scalability is ensured due to the suppression of the supercoupling effect, thus allowing the coexistence of electrons and holes in very thin transistors. Numerical simulations of electrostatics and dynamic operation show how the transient response of this device can be used for dynamic-memory applications, achieving attractive performance in terms of state discrimination and retention time in very scaled devices. View full abstract»

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  • Performance Assessment of Nanoscale Field-Effect Diodes

    Page(s): 2378 - 2384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (842 KB) |  | HTML iconHTML  

    We propose a new structure called a side-contacted field-effect diode (FED). The fabrication of this new structure is simple, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs is presented. The effect of heavy-doping-induced band-gap narrowing on the performance of FEDs is investigated. Our results show that the calculated Ion/Ioff ratio is at least two orders of magnitude larger than that obtained from models neglecting this effect. The figures of merit including intrinsic gate delay time, the energy-delay product, and the subthreshold slope have been studied. Our numerical investigations of the scaling of FEDs indicate that, in the nanometer regime, FEDs have a higher Ion/Ioff ratio. The results demonstrate that FEDs are interesting candidates for future logic applications. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology