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IEEE Transactions on Computers

Issue 2 • Date Feb. 1989

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Displaying Results 1 - 20 of 20
  • A general proof for overlapped multiple-bit scanning multiplications

    Publication Year: 1989, Page(s):172 - 183
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1015 KB)

    Because of recent advances in technology, multibit scanning implementations can be considered that exceed three-bit and four-bit groupings. The generalized proof for the multibit overlapped scanning multiplication is introduced, and the multiplication process is discussed. The proofs are intended to establish the correctness of the decode and the actions taken to produce the multiplication of any ... View full abstract»

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  • On the communication complexity of generalized 2-D convolution on array processors

    Publication Year: 1989, Page(s):184 - 194
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1038 KB)

    Several parallel convolution algorithms for array processors with N/sup 2/ processing elements (PEs) connected by mesh, hypercube, and shuffle-exchange topologies, respectively, are presented. The computation time complexity is the same for array processors with different interconnection networks. The communication time complexity, however, varies from network to network, and is the main focus. It... View full abstract»

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  • On the complexity of single fault set diagnosability and diagnosis problems

    Publication Year: 1989, Page(s):195 - 201
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (765 KB)

    The complexity of the single-fault (SF) set diagnosability and SF-diagnosis problems under the symmetric invalidation models is discussed. It is shown that the SF-diagnosis problem under both these models is co-NP-complete and the SF-diagnosability problem is also co-NP-complete under the asymmetric invalidation model. The SF-diagnosability problem is also studied under the symmetric-invalidation ... View full abstract»

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  • Polynomial testing of packet switching networks

    Publication Year: 1989, Page(s):202 - 217
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1475 KB)

    A functional testing method called polynomial testing is proposed to test packet-switching networks (PSNs) used in multiprocessor systems. Focus is on applying the method to packet-switching multistage interconnection networks (PMINs). A multiple stuck-at (MSA) fault model is developed and faults are diagnosed at two different levels: network level and switch level. The former uses each processor ... View full abstract»

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  • A fault-tolerant mapping scheme for a configurable multiprocessor system

    Publication Year: 1989, Page(s):227 - 237
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1039 KB)

    A fault-tolerant mapping scheme for a configurable multiprocessor system using multistage interconnection networks is presented. By adapting its interprocessor connections, the multiprocessor system can provide many regular topological configurations suitable for a variety of parallel computation applications. The configurability of the system is achieved by applying a set of configuration procedu... View full abstract»

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  • Parallel sorting in two-dimensional VLSI models of computation

    Publication Year: 1989, Page(s):238 - 249
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1354 KB)

    The gradual refinement of a general approach to two-dimensional sorting, the shear-sort algorithm, to more sophisticated and specialized sorting algorithms on mesh-connected computers is described. The analysis of the shear-sort algorithm gives rise to a novel perspective of two-dimensional sorting, which seems to be a very powerful tool for developing efficient algorithms. The same methods can be... View full abstract»

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  • Comments on "Ternary scan design for VLSI testability" by M. Hu and K.C. Smith

    Publication Year: 1989, Page(s):256 - 263
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (553 KB)

    An alternative design is found to be significantly faster than the one proposed by Hu and Smith (see ibid., vol.C-53, p.167-170, (1986)). The performance of the alternative is compared to the original. A means to buffer the signal is presented and its performance is reported. An estimate of silicon area saved versus area spent is made.<> View full abstract»

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  • A DCFL E/D-MESFET GaAs experimental RISC machine

    Publication Year: 1989, Page(s):263 - 274
    Cited by:  Papers (5)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    The design of RCA's 32-bit GaAs microprocessor is described. Technology limitations and influences of the software environment are discussed. The details of the instruction set architecture (ISA) and the instruction execution sequence (IES) are described. The essence of the original contributions of the research and the design is emphasized. The simulated performance evaluation data are presented.... View full abstract»

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  • Partitioning and permuting properties of CC-banyan networks

    Publication Year: 1989, Page(s):274 - 278
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB)

    A multicomputer network, called rectangular CC-banyan, is presented and formally defined. A graph-theoretic approach is used to study this network's permuting and partitioning properties. It is shown that a CC-banyan has a modular structure and hence can be recursively defined. A method for evaluation of the total number of permutations in CC-banyans is presented. Using this method, the analytical... View full abstract»

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  • Optimal matrix multiplication on fault-tolerant VLSI arrays

    Publication Year: 1989, Page(s):278 - 283
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (701 KB)

    A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplying matrices, is described. The algorithm is an efficient simulation of a 2-D systolic algorithm for ... View full abstract»

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  • K-way bitonic sort

    Publication Year: 1989, Page(s):283 - 288
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    The k-way bitonic sort algorithm, a generalization of K.E. Batcher's bitonic sort algorithm (1968), is presented. This variation of the algorithm is based on a k-way decomposition instead of a two-way decomposition. It is proven that Batcher's bitonic sequence decomposition theorem still holds with this multiway decomposition. This leads to applications of sorting networks with bitonic sorters of ... View full abstract»

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  • Fast base extension using a redundant modulus in RNS

    Publication Year: 1989, Page(s):292 - 297
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A technique to extend the base of a residue number system (RNS) based on the Chinese remainder theorem (CRT) and the use of a redundant modulus, is proposed. The technique obtains the residue(s) of a given number in the extended moduli without resorting to the traditional mixed-radix conversion (MRC) algorithm. The base extension can be achieved in log/sub 2/n table lookup cycles, where n is the n... View full abstract»

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  • On the number of permutations performable by extra-stage multistage interconnection networks

    Publication Year: 1989, Page(s):297 - 302
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The number of permutations performable by extra-stage multistage interconnection networks in a single pass is studied. A graph-theoretical approach is used to evaluate the multiplicity of the performable permutations. More specifically, the problem is reduced to a hypercube enumeration problem, and it is shown that there is a direct correspondence between the number of partial subgraphs of a hyper... View full abstract»

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  • The PM221 interconnection network

    Publication Year: 1989, Page(s):302 - 307
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A scheme based on the standard multiplier recoding technique that enables the use of (5*5) switches for PM2I networks is presented. The connections between switching stages are based on the modified PM2I functions, and are called plus-minus-2/sup 2i/ (PM22I); hence, these networks are called the PM22I networks. Since the number of switching stages in the PM22I networks is one-half of those in the ... View full abstract»

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  • Restructuring for fault-tolerant systolic arrays

    Publication Year: 1989, Page(s):307 - 311
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (514 KB)

    The problem of restructuring systolic arrays with faulty cells is considered. An approach to derive the required data-flow paths and computational sites is proposed. The data skewing requirement, which must be satisfied to find an input schedule, is also discussed. Algorithms to restructure systolic arrays for three different architectures of processing elements are presented. A systematic method ... View full abstract»

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  • Analysis of the fork-join queue

    Publication Year: 1989, Page(s):250 - 255
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A fork-join queue is considered as a typical model of parallel processing systems with arrival and departure synchronizations. An approach for obtaining the transient and the steady-state solutions of the fork-join queue in terms of the virtual waiting times, which can be used to obtain the response time and the delay between the fork and the join instants, is presented. With the restriction of th... View full abstract»

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  • Design and analysis of arbitration protocols

    Publication Year: 1989, Page(s):161 - 171
    Cited by:  Papers (29)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    Arbitration protocols are needed to prevent conflicts when several processors share a common resource. Five arbitration protocols, commonly used in digital systems, are modeled and their hardware implementations are discussed. The effect of the chosen protocol on the performance of the system, access time (delay before the bus is available) and data throughput (channel utilization efficiency) for ... View full abstract»

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  • PRAM processor allocation: a hidden bottleneck in sublogarithmic algorithms

    Publication Year: 1989, Page(s):289 - 292
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The problem of dynamic processor allocation in PRAMs (programmable random-access memories) is discussed, and differentiated from that of static allocation. The version of the PRAM considered, also called the CREW model is a parallel computer with global memory accessible in unit time; it allows concurrent reads, but requires exclusive writes. Two dynamic processor allocation problems for ... View full abstract»

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  • A hierarchical computer architecture for distributed simulation

    Publication Year: 1989, Page(s):311 - 319
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    A methodology is developed to map hierarchical, modular discrete-event models onto a distributed simulated architecture, the hierarchical multibus multiprocessor architecture (HM2A). The proposed architecture contains features closely reflecting the structure, behaviour, and modular properties of the model being simulated. Hence, this approach improves on previous approaches, which impo... View full abstract»

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  • A kernel for high-performance multicast communications

    Publication Year: 1989, Page(s):218 - 226
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    A kernel is described, called the link kernel, for high-performance interprocess communication among shared-memory multiprocessors using an Ethernet. The link kernel provides asynchronous multicast communication service without protocol overhead. Links are created by listeners, and processes may be simultaneously talkers and listeners. Processes access links through a global link table. Multicast ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org