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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 6 • Date June 2011

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Displaying Results 1 - 19 of 19
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

    Page(s): 321 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB) |  | HTML iconHTML  

    A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μs without and with the modified bang-bang algorithm, respectively. View full abstract»

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  • A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer

    Page(s): 326 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (681 KB) |  | HTML iconHTML  

    Flying-adder architecture is an emerging on-chip frequency synthesis technology. Its theoretical foundation is the time-average-frequency concept introduced in 2008. During the past decade, the flying-adder technique has been successfully used in numerous commercial products. However, when fractional control word is used, its clock spectrum contains spurious tones due to the periodic carries generated from the fractional accumulation. In this brief, a storage-based technique is introduced to randomize the carries so that the discrete spurs can be converted into noise. View full abstract»

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  • Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

    Page(s): 331 - 335
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a 2-D Markov chain, and the output jitter is smaller than but close to that of a first-order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first-order loop; it is proportional to the clock jitter and inversely proportional to the square root of the stability factor-the ratio of the proportional-path gain to the integral-path gain of the digital loop filter. View full abstract»

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  • A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency

    Page(s): 336 - 340
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    This brief proposes an explicit Dickson charge pump model, including the effect of the resistance of switching devices on the pump performance. Using this model, one can estimate an optimum clock frequency and the size of the transferring transistors in terms of the main pump capacitors, the auxiliary capacitors, and the transfer transistors to maximize the output current under the same silicon area in a given technology. View full abstract»

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  • Predicting and Avoiding Spurious Tones in a DWA-Mismatch-Shaping DAC

    Page(s): 341 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (339 KB) |  | HTML iconHTML  

    A data-weighted-averaging (DWA) algorithm provides a simple realization of the first-order mismatch shaping of digital-to-analog-converter (DAC) errors. A drawback of DWA is the tendency for generating spurious tones. This brief proposes an analytical model for mismatch-noise tone behavior. The model explains how the spurious tones depend on the stimulus and the DAC error shape. It is also shown that the in-band spurious tones can be minimized by altering the differential-nonlinearity-error shape simply by rearranging the unit elements. View full abstract»

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  • High-Order Mismatch-Shaping in Multibit DACs

    Page(s): 346 - 350
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB) |  | HTML iconHTML  

    This brief reports a high-order mismatch-shaping technique for multibit ΔΣ digital-to-analog converters (DACs). It builds upon the vector-based method but with two key improvements. First, a new vector quantization (VQ) scheme exploits the information in all vector variables. This VQ scheme allows the second-order mismatch shaping for large input signals and makes possible the stable third- and fourth-order mismatch shaping. Second, a hardware-efficient method maintains the average of the vector variables bounded. Simulations under various conditions prove its validity. View full abstract»

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  • A Subhertz Nanopower Low-Pass Filter

    Page(s): 351 - 355
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    This brief presents a first-order low-pass filter topology capable of providing cutoff frequencies down to 2 mHz with power consumption of 5 nW. The circuit is intended for signal conditioning applications, particularly for use with very low frequency physiological signals in low-power portable medical equipment. To achieve a low-frequency cutoff, the filter is based around the use of a clocked transconductor, which provides low transconductance while using a relatively high bias current level. The circuit is implemented in a 0.35-μm technology with a 1-V supply and has 32- μVRMS measured noise and a 64-dB dynamic range. In terms of power consumption and cutoff frequency the reported filter outperforms previous filters from the literature. View full abstract»

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  • An Electronically Fine-Tunable Multi-Input–Single-Output Universal Filter

    Page(s): 356 - 360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB) |  | HTML iconHTML  

    A new electronically fine-tunable multi-input-single-output (MISO) universal filter is proposed. The filter circuit compared with active-device-based counterparts is very simple and fully integrable. Moreover, a few number of active transistors provide a reduction in power consumption, and the filter enjoys advantages such as no component matching and small size area. Postlayout simulation results using parameters of AMS CMOS 0.35-μm process technology show good agreement with theoretical expectations. View full abstract»

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  • A Spread Spectrum Clock Generator for DisplayPort Main Link

    Page(s): 361 - 365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB) |  | HTML iconHTML  

    This brief presents a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link. The process variation compensator reduces the error of spread ratio and guarantees reliable operation of an SSCG. The test chip has been implemented in 0.18-μm complementary metal-oxide-semiconductor process. The SSCG supports 10-phase 270- and 162-MHz clocks. The phase noise of an output clock at 270 MHz without spread spectrum clocking is -97.7 and -120.4 dBc/Hz at 1- and 10-MHz offset, respectively. The peak reduction is 8.75 dBm, and the spread ratio of 5000 ppm is achieved with a process variation compensator. View full abstract»

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  • Regularization of the Affine Projection Algorithm

    Page(s): 366 - 370
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    The affine projection algorithm (APA) is an attractive choice for echo cancellation, mainly for its convergence features. A matrix inversion is required within the APA. For practical reasons, this matrix needs to be regularized, i.e., a positive constant is added to the elements of its main diagonal. This regularization parameter is of great importance in practice since, if it is not chosen properly, the APA may never converge, especially under low-signal-to-noise-ratio conditions. In this brief, we propose a formula for choosing the value of the regularization parameter, aiming at attenuating the effects of the noise in the adaptive filter estimate. Simulations performed in an acoustic echo cancellation scenario prove the validity of the approach in different noisy environments. View full abstract»

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  • A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals

    Page(s): 371 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    Low-complexity and flexible spectrum sensing is one of the challenging tasks in a cognitive radio (CR). Most of the work on energy-detection-based spectrum sensing presented in the literature employ a filter bank (FB) to split the wideband input signal into several subbands and detect the spectrum by computing the energy of subbands. However, for a mobile CR handset, a filter-bank-based spectrum sensing is not an area- and power-efficient scheme. In this paper, a novel spectrum-sensing scheme based on a reconfigurable digital downconverter (RDDC) and a reconfigurable filter based on coefficient decimation is proposed for mobile CR handsets, which has very low complexity and high flexibility compared to conventional FB approaches. The basic idea is to rotate the spectrum using an RDDC and filter the desired portion of the spectrum using the reconfigurable filter, which then results in very low complexity. The implementation results on Virtex-4 field-programmable gate array show that our method offers significant reductions in gate count, power consumption, and delay over conventional discrete Fourier transform FB-based spectrum sensing. View full abstract»

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  • Design of a Monolithic Automatic Substrate/Supply Multiplexer for DVS-Enabled Adaptive Power Converters

    Page(s): 376 - 380
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    It allows the converters to seamlessly regulate the output voltage at any desired level without suffering large leakage current and latch-up. In addition, an automatic supply voltage multiplexing scheme is presented to significantly improve power efficiency and reduce chip area. The proposed ASSM circuit was fabricated with an IBM 130-nm CMOS process. Experimental results show a 4.44-mV/ns switching speed with a switching voltage ranging from 0.9 to 2.5 V. Due to an accurate voltage comparison, the tracking error in steady state is effectively minimized below 5 mV. The circuit only occupies a 0.015-mm2 silicon area, with maximum static power of 227 μW. View full abstract»

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  • Study of Periodic Solutions in Discretized Two-Dimensional Sliding-Mode Control Systems

    Page(s): 381 - 385
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (391 KB) |  | HTML iconHTML  

    The existence of periodic solutions in discretized 2-D equivalent control-based sliding-mode control systems is studied. Admissibility conditions for the existence of periodic solutions with specific symbol sequences are derived, and admissibility regions for short periodic sequences are found. It is shown that, for certain parameter values, there exist arbitrarily long periodic orbits for arbitrarily small discretization steps. Theoretical results are illustrated with simulation examples. View full abstract»

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  • Passivity-Based Integral Sliding-Mode Control of Uncertain Singularly Perturbed Systems

    Page(s): 386 - 390
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    This brief is concerned with passivity-based integral sliding-mode control of uncertain singularly perturbed systems. First, a proper integral sliding surface is constructed. Then, a sufficient condition in terms of linear matrix inequality (LMI) is derived under which the resulting closed-loop system is passive and asymptotically stable in the specified switching surface. The gain matrix of the sliding mode is achieved by means of the previous LMI. In addition, a sliding-mode controller is synthesized to guarantee the reachability of the specified sliding surface. Finally, a numerical example is provided to illustrate the effectiveness of the developed theoretical results. View full abstract»

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  • 2011 IEEE membership form

    Page(s): 391 - 392
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope