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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 7 • Date July 2011

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Displaying Results 1 - 25 of 27
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • Guest Editorial Special Issue on ISCAS 2010

    Publication Year: 2011 , Page(s): 1457
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  • A Low Power Impulse Radio Design for Body-Area-Networks

    Publication Year: 2011 , Page(s): 1458 - 1469
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1818 KB) |  | HTML iconHTML  

    This paper presents a low power radio design tailored to the short distance, low data rate application of body area networks. In our analysis we consider a comparison between traditional continuous wave radios and ultra wide band impulse radios for this application space. We analyze the energy/bit requirement for each of the architectures and discuss how a duty-cycled radio is better suited to low data rate applications due to practical design considerations. As a proof-of-concept we present the design and measured results of a duty-cycled, noncoherent impulse radio transceiver. The designed transceiver was measured to consume only 19 μW at a data-rate of 100 kbps. The design gives a BER of 10-5 and works for a range of 2.5 m at an average Rx-sensitivity of -81 dBm. The designed transceiver enables both OOK and BPSK schemes and can be configured to use a pseudocoherent self-correlated signature detection and generation mechanism. This added functionality helps distinguish different types of pulses such as timing and data-pulses in real time. The transceiver was designed in a 90 nm CMOS process and occupies 2.3 mm2 area. View full abstract»

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  • A Low-Power and Flexible Energy Detection IR-UWB Receiver for RFID and Wireless Sensor Networks

    Publication Year: 2011 , Page(s): 1470 - 1482
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2614 KB) |  | HTML iconHTML  

    This paper presents an energy detection Impulse Radio Ultra-Wideband (IR-UWB) receiver for Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSN) applications. An Application-Specific Integrated Circuit (ASIC) consisting of a 3-5 GHz analog front-end, a timing circuit and a high speed baseband controller is implemented in a 90 nm standard CMOS technology. A Field-Programmable Gate Array (FPGA) is employed as a reconfigurable back-end, enabling adaptive baseband algorithms and ranging estimations. The proposed architecture is featured by high flexibility that adopts a wide range of pulse rate (512 kHz-33 MHz), processing gain (0-18 dB), correlation schemes, synchronization algorithms, and modulation schemes (PPM/OOK). The receiver prototype was fabricated and measured. The power consumption of the ASIC is 16.3 mW at 1 V power supply, which promises a minimal energy consumption of 0.5 nJ/bit. The whole link is evaluated together with a UWB RFID tag. Bit error rate (BER) measurement displays a sensitivity of -79 dBm at 10 Mb/s with 10-3 BER achieved by the proposed receiver, corresponding to an operation distance over 10 meters under the FCC regulation. View full abstract»

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  • On Pulse Position Modulation and Its Application to PLLs for Spur Reduction

    Publication Year: 2011 , Page(s): 1483 - 1496
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (924 KB) |  | HTML iconHTML  

    Randomizing the positions of charge pump current pulses in a PLL breaks their periodicity and redistributes the reference spurs into broadband noise. Closed form expressions for the power spectral density (PSD) of pulse position modulated (PPM) signals are derived and intuitive explanations for the results are given. The redistributed noise has a high-pass shape and does not affect the close in phase noise of the PLL. PPM using a uniformly distributed i.i.d. sequence completely removes the spurs and provides a first-order shaping of redistributed noise. Higher order shaping and reduction of redistributed noise at intermediate offset frequencies are possible using PPM with a high-pass shaped modulating sequence and pulse repetition. Circuit implementations of these techniques are given and their nonidealities are discussed. Simulation results from a 1 GHz PLL operating from a reference frequency of 20 MHz and a bandwidth of 1 MHz confirm the results of the analysis and viability of the proposed techniques. In the presence of nonidealities spurs can be reduced by at least 13 dB without any trimming of the delays in the PPM circuits and by 25 dB after trimming the delays to within 5% of the nominal value. View full abstract»

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  • State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

    Publication Year: 2011 , Page(s): 1497 - 1510
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1208 KB) |  | HTML iconHTML  

    The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers. View full abstract»

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  • A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

    Publication Year: 2011 , Page(s): 1511 - 1517
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (870 KB) |  | HTML iconHTML  

    This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (P&R) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm2. View full abstract»

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  • Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay

    Publication Year: 2011 , Page(s): 1518 - 1530
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1603 KB) |  | HTML iconHTML  

    Novel implementation techniques, such as the use of direct-charge-transfer stage, noise coupling, and dynamic element matching can improve the performance of wideband ΔΣ ADCs. However, they introduce extra loop delay, which compromises the low-distortion property and even the loop stability. This paper shows how the addition of independent feedback and feed-forward branches to the loop filter can compensate the extra loop delay, and restore the desired signal and noise transfer functions. The design methodology is then generalized for different kinds of ΔΣ ADCs, and the low-distortion property is analyzed. Two wideband delta-sigma ADCs have been designed and simulated to verify the theory. View full abstract»

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  • A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters

    Publication Year: 2011 , Page(s): 1531 - 1541
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1912 KB) |  | HTML iconHTML  

    This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 μm CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology. View full abstract»

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  • A Sub-500 mV Highly Efficient Active Rectifier for Energy Harvesting Applications

    Publication Year: 2011 , Page(s): 1542 - 1550
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB) |  | HTML iconHTML  

    This paper presents a highly efficient, ultra-low-voltage active full wave rectifier. A two-stage concept is used including a first passive stage and only one active diode as second stage. A bulk-input comparator working in the subthreshold region is used to drive the switch of the active diode. The voltage drop over the rectifier is some tens of millivolt, which results in voltage and power efficiencies of over 90%. The design was successfully implemented in an 0.35 μm CMOS technology. The measured power consumption of the comparator is 266 nW@500 mV and the minimum operating voltage is 380 mV. Input voltages with frequencies up to 10 kHz can be rectified. View full abstract»

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  • Harvesting Ambient Kinetic Energy With Switched-Inductor Converters

    Publication Year: 2011 , Page(s): 1551 - 1560
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB) |  | HTML iconHTML  

    The potential application space for miniaturized systems like wireless microsensors is expansive, from reconnaissance mission work and remote sensors to biomedical implants and disposable consumer products. Conforming to microscale dimensions, however, constrains energy and power to such an extent that sustaining critical power-hungry functions like wireless communication is problematical. Harvesting ambient kinetic energy offers an appealing alternative, except the act of transferring energy requires power that could easily exceed what the harvester generates in the first place. This paper reviews piezoelectric and electrostatic harvester circuits, describes how to design low-power switched-inductor converters capable of producing net energy gains when supplied from piezoelectric and electrostatic transducers, and presents experimental results from prototype embodiments. In the electrostatic case shown, the controller dissipated 0.91 nJ per cycle and the switched-inductor precharger achieved 90.3% efficiency to allow the harvester to net a gain of 2.47 nJ per cycle from a capacitor that oscillated between 157 and 991 pF. The piezoelectric counterpart harnessed 1.6 to 29.6 μW from weak periodic vibrations with 0.05-0.16- m/s2 accelerations and 65.3 μJ from (impact-produced) nonperiodic motion. View full abstract»

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  • A 400 \mu W Hz-Range Lock-In A/D Frontend Channel for Infrared Spectroscopic Gas Recognition

    Publication Year: 2011 , Page(s): 1561 - 1568
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (835 KB) |  | HTML iconHTML  

    This paper presents a low-power and fully integrated frontend channel for long-wave infrared spectroscopic gas recognition. The proposed channel circuitry includes: input sensor biasing, sub-Hz high-pass filtering and pre-amplification, differential blind cancellation, and lock-in A/D conversion. The proposed CMOS circuits make extensive use of transistor subthreshold operation and digital programmability. Experimental results are presented for a 0.3 mm2 400 μW channel prototype integrated in 0.35 μm CMOS technology. View full abstract»

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  • A CMOS Single-Chip Gas Recognition Circuit for Metal Oxide Gas Sensor Arrays

    Publication Year: 2011 , Page(s): 1569 - 1580
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2379 KB) |  | HTML iconHTML  

    This paper presents a CMOS single-chip gas recognition circuit, which encodes sensor array outputs into a unique sequence of spikes with the firing delay mapping the strength of the stimulation across the array. The proposed gas recognition circuit examines the generated spike pattern of relative excitations across the population of sensors and looks for a match within a library of 2-D spatio-temporal spike signatures. Each signature is drift insensitive, concentration invariant and is also a unique characteristic of the target gas. This VLSI friendly approach relies on a simple spatio-temporal code matching instead of existing computationally expensive pattern matching statistical techniques. In addition, it relies on a novel sensor calibration technique that does not require control or prior knowledge of the gas concentration. The proposed gas recognition circuit was implemented in a 0.35 μm CMOS process and characterized using an in-house fabricated 4 × 4 tin oxide gas sensor array. Experimental results show a correct detection rate of 94.9% when the gas sensor array is exposed to propane, ethanol and carbon monoxide. View full abstract»

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  • Event-Based Pixel Sensitive to Changes of Color and Brightness

    Publication Year: 2011 , Page(s): 1581 - 1590
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1594 KB) |  | HTML iconHTML  

    Vision sensors whose pixels asynchronously generate informative output events are gathering increasing interest because they can reduce the data latency, rate, and redundancy, while also increasing dynamic range. This paper proposes such a dynamic vision sensor (DVS) pixel which is aimed at color vision (cDVS). The pixel combines subthreshold continuous time analog circuits with event-driven switched capacitor amplifiers and asynchronous digital outputs. The cDVS simultaneously detects separate log-intensity and wavelength change events using a single buried double junction (BDJ) photodiode. Chip measurements show that the cDVS color change pathway can detect light wavelength changes as small as 15 nm while the cDVS relative intensity change pathway detects changes as small as 10% of intensity. The circuit is characterized and improvements are proposed. View full abstract»

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  • A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

    Publication Year: 2011 , Page(s): 1591 - 1603
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1735 KB) |  | HTML iconHTML  

    A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown. View full abstract»

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  • Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design

    Publication Year: 2011 , Page(s): 1604 - 1614
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1215 KB) |  | HTML iconHTML  

    Floating-gate and quasi-floating gate MOS transistors can be efficiently employed to design CMOS transconductors. These transistors allow achievement of relevant features in a compact and simple way, such as rail-to-rail input range, continuous transconductance tuning, and class AB operation. This paper illustrates how these techniques can be applied by employing them in the design of two transconductors, which have been fabricated in a 0.5 μm CMOS process. Measurement results confirm the advantages of the proposed approach. View full abstract»

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  • Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

    Publication Year: 2011 , Page(s): 1615 - 1626
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive I-V characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 μm CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz. View full abstract»

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  • Design of Discrete-Valued Linear Phase FIR Filters in Cascade Form

    Publication Year: 2011 , Page(s): 1627 - 1636
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2209 KB) |  | HTML iconHTML  

    Digital filters in cascade form enjoy many advantages over their equivalent single-stage realizations in that lower coefficient sensitivity, higher throughput, reduced computational and smaller implementation cost can be achieved. However, the numerical design and optimization of such structure are of much more difficulty than the single-stage case if the filter coefficients are restricted to be of discrete values. This is mainly due to the non-convexity of the constraints, which rules out the possibility of employing sophisticated convex optimization techniques as well as the guaranteed global optimality. In this work, a general-purpose algorithm is proposed for the design of linear phase finite impulse response (FIR) filters in cascade form with discrete coefficients. The proposed algorithm decomposes the overall filter into subfilters during the traverse of a tree search of the overall filter. Discrete-valued linear phase FIR filters are able to be searched and decomposed into both symmetric and non-symmetric subfilters. The optimization complexity is of the same order as the single-stage filter optimization. Design examples have shown that the proposed algorithm is capable of achieving notable reduction in both implementation cost and adder depth compared with their single-stage optimum designs. View full abstract»

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  • On the Synchronization Condition for Superharmonic Coupled QVCOs

    Publication Year: 2011 , Page(s): 1637 - 1646
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB) |  | HTML iconHTML  

    A steady-state nonlinear analysis of quadrature voltage-controlled oscillators (QVCOs) comprising two VCOs mutually coupled at their second-harmonic frequency through a direct coupling circuit is presented. The analysis is based on an accurate prediction of the behavior of each VCO, which is analyzed separately as an injection locked oscillator taking into account both higher order harmonics of the differential tank voltage and the effect of the common-mode voltage at the drain terminals. We show that synchronization of the two VCOs is possible only at a frequency, derived in closed-form, which differs appreciably from the tank's resonant frequency. View full abstract»

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  • A Bio-Inspired Cochlear Heterodyning Architecture for an RF Fovea

    Publication Year: 2011 , Page(s): 1647 - 1660
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1566 KB) |  | HTML iconHTML  

    We discuss the use of cochlear models for spectrum analysis at radio frequencies. We describe performance characteristics of such models, including noise, dynamic range, and frequency resolution. We show that the addition of phase information improves frequency estimation as compared to the use of amplitude information alone. In particular, the use of both amplitude and phase information in a novel nonlinear bio-inspired center-surround coincidence-detection stage simultaneously improves frequency estimation and implements a lowpass-to-bandpass transformation on cochlear outputs. In order to further improve frequency estimation we propose a novel wireless receiver architecture that is a broadband generalization of narrowband heterodyning systems commonly used in radio. We term this architecture cochlear heterodyning. It exploits the efficiency of cochlear spectrum analysis to perform parallel, multi-scale analysis of wideband signals and can be constructed with cochlea-like traveling-wave structures. When combined with our prior work on an RF cochlea, such architectures may be useful in cognitive radios for creating RF foveas that select narrowband components present within wideband, but spectrally sparse signals. The operation of RF foveas is analogous to how the eye foveates on narrow but interesting portions of an image. Analogies between spectrum analysis and the process of successive-subranging analog-to-digital conversion illustrate how successively finer frequency resolution is achieved in an RF fovea. Finally, we show that RF foveas can be used in feedback loops to perform interference cancellation. View full abstract»

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  • Type-Based Group Delay Equalization Technique

    Publication Year: 2011 , Page(s): 1661 - 1670
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2581 KB) |  | HTML iconHTML  

    This paper presents a patented type-based group- delay equalization technique to compensate for in-band group- delay distortion typically existing in analog/RF filter circuits. The underlining principle is that for a given modulation scheme and pulse-shaping function, the modulated signal has a unique statistical distribution, and that when the modulated signal passes through a circuit, any in-band group-delay distortion in the circuit distorts its output statistical distribution. The technique employs an equalization filter to minimize the in-band group-delay distortion, with the filter coefficients derived from a measure of the distortion in the output statistical distribution using a weighted nonlinear least square algorithm. It requires simple analog and digital hardware and firmware to implement, and its implementation is inherently adaptive, capable of tracking and compensating for any variation in the group-delay distortion characteristic due to component aging and temperature variation. Computer simulations have been performed to show that an accurate equalization filter can be obtained to effectively compensate for the group-delay distortion, achieving significant performance improvements. View full abstract»

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  • Dual Modulation Technique for High Efficiency in High-Switching Buck Converters Over a Wide Load Range

    Publication Year: 2011 , Page(s): 1671 - 1680
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1785 KB) |  | HTML iconHTML  

    A dual modulation technique to improve power conversion efficiency with minimal increase in output voltage ripple is presented. The worsening switching noise caused by parasitic resistance and inductance due to high-switching operation can also be alleviated by the proposed ac ripple detector. Furthermore, the dual modulation method can speed up the load transient response since the switching frequency can increase to 5 MHz during the transient period. At very light loads, the switching frequency is always kept higher than the acoustic frequency to avoid noisy sound. Experiment results show that the converter operates at 5 MHz using a small inductor of 1 μH. The load transient response time is shorter than 3 μs when load current changes from 150 to 450 mA or vice versa. Power efficiency is kept higher than 85% over a wide load current range. Specifically, light efficiency can be raised to about 45% above that of the conventional design. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2011 , Page(s): 1681
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2011 , Page(s): 1682
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras