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Circuits, Devices and Systems, IEE Proceedings G

Issue 4 • Date Aug 1993

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Displaying Results 1 - 11 of 11
  • Complementary transistor technology for use in optoelectronic integrated circuits

    Publication Year: 1993 , Page(s): 279 - 284
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    A new compound semiconductor complementary transistor technology is proposed and the constituent devices demonstrated in discrete form. The n-channel transistor exhibits a peak transconductance of 110 mS/mm, a drain current density of 24 0 mA/mm and a unity current gain frequency of 9.5 GHz for a nominal gate length of 1 μm. The p-channel transistor has a peak transconductance of 35 mS/mm and a drain current density of 65 mA/mm for an effective gate length of 1.1 μm. Compatibility of this technology with optical devices is shown by fabricating a laser from the same material. Threshold current densities as low as 950 A/cm2 and external efficiencies of 50% are obtained View full abstract»

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  • General-purpose parallel hardware approach to the routing problem of VLSI layout

    Publication Year: 1993 , Page(s): 294 - 304
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1028 KB)  

    A novel solution to the important problem of speeding up the routing process in integrated circuit (IC) design, involving the use of general-purpose parallel computing hardware, is introduced. In the past, attempts to speed up any one stage of the VLSI design process have often resulted in a very expensive, dedicated piece of hardware which cannot be used to speed up other phases of the design process. In the case of routing, dedicated hardware has been designed to accelerate specifically the maze routing algorithm, which is more useful for routing PCBs rather than VLSI designs. As more general-purpose parallel hardware has become available, especially in the form of workstations, there has been an increasing need to exploit parallelism in many computationally intensive applications. The authors address the problem of exploiting parallelism in the computationally intensive problem of routing for VLSI design. This is performed hierarchically and involves two stages: global and detailed routing. A parallel routing framework was proposed to fit into such a structure. Not only some of the ideas in the framework but also a general evaluation of the different parts of the framework are presented View full abstract»

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  • Discrete approximation of continuous-time systems: a survey

    Publication Year: 1993 , Page(s): 264 - 278
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1184 KB)  

    A survey of techniques suitable for discrete approximation of continuous-time systems is presented. Most of them are assigned to two groups in which the F-transformation is utilised either directly or indirectly. The direct approach includes the time-response invariance methods, the forming element techniques, the convolution approximation and the stochastic matching methods. From among the indirect procedures, the integrating operator methods distinguish themselves. They can be used in simple or expanded versions. Roots selection and transformations using inverse approximations are also related to the indirect or partial matching technique. There is a class of normal transformations which have the common feature of employing Chebyshev functions. Stable forms of normal interpolators and integrating operators, and a piecewise-normal approximation are useful in the derivation of discrete-time state-space models View full abstract»

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  • Multiple objective optimisation in a behavioural synthesis system

    Publication Year: 1993 , Page(s): 253 - 260
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    The authors describe the implementation of an `intelligent' silicon compiler that provides the ability to optimise a design, given as a behavioural description, with respect to multiple objectives. The user submits goals or objectives to the system, named MOODS, which automatically finds an optimal solution in the context of the user-specified constraints. The MOODS system provides a sound basis for multiple objective optimisation and allows the user to characterise and explore the design space. An accurate representation of the implementations in the design space is ensured by feeding up technology-dependent information from a cell library. This data is used in a global cost function which guides the application of transformations on a multilevel representation of the design. The results obtained show that designs can be produced which meet users' objectives and that a varied set of implementations can be synthesised from a single behavioural specification. The resulting characteristics of the set of implementations enable the design space to be characterised View full abstract»

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  • Self-purging redundancy with automatic threshold adjustment

    Publication Year: 1993 , Page(s): 233 - 236
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A self-purging system is proposed which uses a digital voter that automatically adjusts the threshold of the voter as failed modules are purged. The switch used is no more complex than the switch used by the self-purging redundancy proposed by Losq (1976). However, the system presented here can tolerate single module failures at any given time. This system is useful for applications in which aging or stress is the cause of failure rather than noise View full abstract»

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  • Electron drift velocity model for simulation of InGaAs JFETs

    Publication Year: 1993 , Page(s): 261 - 263
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    Simulations of InGaAs JFETs were carried out using a two-dimensional numerical simulator. The results show that the electron drift velocity field characteristic is very important in modelling the Id/Vds behaviour of these devices. From comparison with experimental results, the authors conclude that it is appropriate to use a velocity field dependence function for InGaAs, similar to the drift velocity function used for Si JFETs View full abstract»

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  • Theoretical prediction of the performance of Si and SiC bipolar transistors operating at high temperatures

    Publication Year: 1993 , Page(s): 289 - 293
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    Silicon carbide (SiC) is a promising material for semiconductor devices operated at high temperatures because of its large energy bandgap, high thermal conductivity and silicon compatibility. The authors develop an analytical model to predict and compare the DC and AC performance of SiC and conventional Si bipolar junction transistors (BJTs) at high temperatures. Based on the device parameters available in the literature, the authors' calculations show that the SiC BJT indeed possesses a higher current gain than its silicon counterpart as the temperature is increased beyond 500 K. This is primarily because SiC has a larger bandgap than Si. As a result, at high temperatures, the majority carrier concentration in the base of the SiC BJT remains the same value as the doping concentration, whereas the majority carrier concentration in the base of the Si BJT increases considerably beyond the doping concentration. The cutoff frequency of the SiC BJT, however, decreases and becomes smaller than that of the Si BJT when the temperature increases. The authors suggest this is caused by a faster decrease in the electron mobility of SiC than of Si as the temperature is increased. The model compares favourably with data measured from a typical Si BJT View full abstract»

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  • New designs for a sign detector and a residue to binary convertor

    Publication Year: 1993 , Page(s): 247 - 252
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    In this paper, two algorithms have been developed. The first one has been exploited in implementing a residue to binary convertor (R/B) for the moduli set {2k-1, 2k, 2k+1}. The new convertor is memoryless, which implies that its upper bound is not limited by a memory size. Furthermore, this convertor represents a new significant reduction in both the hardware requirements and conversion time. A full conversion cycle consists of three consecutive additions each of (k+1) bits. The same implementation can be modified slightly to implement a sign detector for the same moduli set. Another algorithm has been developed based on the mixed radix conversion technique. This algorithm was used to implement a new sign detector. This new detector is very efficient in the sense that it requires only two addition cycles each of (k+1) bits. A further reduction in execution time is possible if pipelining is used. All the circuits presented can be implemented using VLSI technology, which gives rise to a reduction in the integrated circuit area View full abstract»

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  • Chebyshev phase of IIR networks for pulse expanding

    Publication Year: 1993 , Page(s): 285 - 288
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The author describes a method for designing IIR allpass circuits for pulse expanding, the phase of which approximates to a squared phase in the Chebyshev sense in the given frequency region. The method is based on the solution of a linear equation system which provides a final solution with a very small number of iterative cycles View full abstract»

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  • Cascade pseudomultibit noise shaping modulators

    Publication Year: 1993 , Page(s): 237 - 246
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    Cadcade and multibit quantisation 1-bit feedback (NA/D1) noise shaping modulators are presently considered the most attractive topologies for implementing high resolution A/D convertors. This is because the cascade concept allows stable high order noise shaping modulators to be implemented easily, and because the NA/D1 architecture allows the amount of quantisation noise handled to be reduced while avoiding the disadvantages of using N-bit D/A convertors (N ⩾2). The authors propose that cascade and multibit modulators should be seen as particular cases in a wider modulator architecture, here referred to as GaMeS. The design methodology proposed also permits several new modulators to be derived. All of them allowed the authors to explore the three parameters in the design of an A/D convertor, which are the oversampling ratio, M, the noise shaping order, L , and the quantiser resolution, N. An analytical study is made of integrator gain and pole error effects in the SNR performance, as well as of nonidealities present in N-bit quantisers. Simulations made with a user-friendly and behavioural simulator developed by the authors, prove the correctness of the analyses made, and indicate that high resolution wideband A/D convertors can take advantage of these new topologies View full abstract»

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  • Ambient temperature effects on DC behaviour of GaAs MESFET devices

    Publication Year: 1993 , Page(s): 305 - 311
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    DC measurements at different temperatures on a wide range of different-sized MESFET devices show that temperature effects change the behaviour of the device. The results indicate that, as the drain current is reduced, the behaviour of the device becomes more susceptible to temperature effects. In the main, this is due to the temperature dependency of the pinchoff point. The data presented show that the dependency of the pinchoff point on temperature does not follow a straight-line law, but has three regions of operation, each with a different temperature coefficient. The data also show that, as the temperature is reduced, the dependency of the pinchoff point on the drain-source voltage increases View full abstract»

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