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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2011, Page(s): C2
| PDF (40 KB)
• ### Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms

Publication Year: 2011, Page(s):1125 - 1135
Cited by:  Papers (13)  |  Patents (1)
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This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and back-end signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be r... View full abstract»

• ### Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers

Publication Year: 2011, Page(s):1136 - 1146
Cited by:  Papers (35)
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This paper presents a systematic design approach to provide the optimized Rivest-Shamir-Adleman (RSA) processors based on high-radix Montgomery multipliers satisfying various user requirements, such as circuit area, operating time, and resistance against side-channel attacks. In order to involve the tradeoff between the performance and the resistance, we apply four types of exponentiation algorith... View full abstract»

• ### Delay-Based Dual-Rail Precharge Logic

Publication Year: 2011, Page(s):1147 - 1153
Cited by:  Papers (15)
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This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rat... View full abstract»

• ### Prediction and Comparison of High-Performance On-Chip Global Interconnection

Publication Year: 2011, Page(s):1154 - 1166
Cited by:  Papers (12)
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As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global intercon... View full abstract»

• ### Adaptive Power Control Technique on Power-Gated Circuitries

Publication Year: 2011, Page(s):1167 - 1180
Cited by:  Papers (3)
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An adaptive power control (APC) system on power-gated circuitries is proposed. The core technique is a switching state determination mechanism as an alternative of critical path replicas. It is intrinsically tolerant of process, voltage, and temperature (PVT) variations because it directly monitors the behavior of VDDV node. The APC system includes a multi-mode power gating network, a voltage sens... View full abstract»

• ### IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs

Publication Year: 2011, Page(s):1181 - 1191
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IR-drop management in the power supply network of a chip is one of the critical design challenges in nanometer VLSI circuits. Techniques developed for application-specific integrated circuits cannot be directly applied for IR drop management in field-programmable gate arrays (FPGAs) because of the programmable nature of FPGAs. This paper proposes a novel clustering technique for improving the supp... View full abstract»

• ### Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-$kappa$ Metal-Gate Devices

Publication Year: 2011, Page(s):1192 - 1204
Cited by:  Papers (25)
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The threshold voltage (VTH) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term VTH drifts degrade SRAM cell stability, margin, and performance, and may lead to functional failure over the life of usage. Meanwhile, the contact resis... View full abstract»

• ### Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions

Publication Year: 2011, Page(s):1205 - 1217
Cited by:  Papers (7)
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This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The methodology is based on small-signal analyses performed at the individual analog and digital microcontroller building block level, on electromagnetic si... View full abstract»

• ### A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

Publication Year: 2011, Page(s):1218 - 1228
Cited by:  Papers (7)
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This study proposes a high precision fast locking arbitrary duty cycle clock synchronization (HPCS) circuit. This HPCS is capable of synchronizing the external clock and the internal clock in three clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control c... View full abstract»

• ### Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes

Publication Year: 2011, Page(s):1229 - 1238
Cited by:  Papers (51)  |  Patents (3)
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Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding... View full abstract»

• ### An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation

Publication Year: 2011, Page(s):1239 - 1248
Cited by:  Papers (1)
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Motion estimation (ME) consumes up to 70% of the entire video encoder's computations and is, therefore, the main encoding-time consuming process. Discrete cosine transform (DCT)-based phase correlation along with dynamic padding (DP) are the recently evolved frequency domain ME (FDME) techniques that promise to efficiently reduce the computational complexity of the ME process. DP uses dynamic padd... View full abstract»

• ### Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis

Publication Year: 2011, Page(s):1249 - 1262
Cited by:  Papers (1)
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This paper presents an effective design methodology which maps a complex system represented as a dataflow graph to a reconfigurable target architecture having multi-core processors and programmable logics. In order to synchronize data transfers between two processing blocks mapped to different processors (alternatively, one block is mapped to a processor and the other is realized as a hardware), w... View full abstract»

• ### A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

Publication Year: 2011, Page(s):1263 - 1276
Cited by:  Papers (21)
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New generation embedded systems demand high performance, efficiency, and flexibility. Reconfigurable hardware can provide all these features. However, the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfi... View full abstract»

• ### Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction

Publication Year: 2011, Page(s):1277 - 1290
Cited by:  Papers (4)
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We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits without appreciable increase in wire length (WL). FlowPlace includes: 1) a timing-driven (TD) analytical global placer TAN that uses accurate pre-route delay functions and minimizes a combination of linear and quadratic objective functions; 2) a dis... View full abstract»

• ### A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement

Publication Year: 2011, Page(s):1291 - 1304
Cited by:  Papers (3)
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In this paper, we propose an effective white-space (i.e., row length) constraint satisfaction technique embedded in a network flow based detailed placer for standard cell designs that is suitable for both incremental as well as full detailed placement. The highlight of our method is a provable high-probability of obtaining a legal placement even under tight white space (WS) constraints. This high ... View full abstract»

• ### A Sub-1 V, 26 $mu$W, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode

Publication Year: 2011, Page(s):1305 - 1309
Cited by:  Papers (13)
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We present a low-power bandgap reference (BGR), functional from sub-1 V to 5 V supply voltage with either a low dropout (LDO) regulator or source follower (SF) output stage, denoted as the LDO or SF mode, in a 0.5-μm standard digital CMOS process with Vtn ≈ 0.6 V and |Vtp| ≈ 0.7 V at 27°C. Both modes operate at sub-1 V under zero load... View full abstract»

• ### A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 $mu$s Frequency Acquisition Time

Publication Year: 2011, Page(s):1310 - 1315
Cited by:  Papers (3)
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This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance.... View full abstract»

• ### Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS

Publication Year: 2011, Page(s):1315 - 1319
Cited by:  Papers (22)
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Deep sub-micrometer/nano CMOS circuits are more sensitive to externally induced radiation phenomena that are likely to cause the occurrence of so-called soft errors. Therefore, the tolerance of the circuit to the soft errors is a strict requirement in nanoscale circuit designs. Since the traditional error tolerant methods result in significant cost penalties in terms of power, area, and performanc... View full abstract»

• ### Aggressive Runtime Leakage Control Through Adaptive Light-Weight $V_{rm th}$ Hopping With Temperature and Process Variation

Publication Year: 2011, Page(s):1319 - 1323
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The increasing leakage power consumption and stringent thermal constraint necessitate more aggressive leakage control techniques. Power gating and body biasing are widely used for standby leakage control. Their large energy overhead for performing mode transition is the major obstacle for more aggressive leakage control. Temperature and process variation (TV/PV) further magnify the overhead proble... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

Publication Year: 2011, Page(s): 1324
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2011, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu