Scheduled System Maintenance
On Friday, October 20, IEEE Xplore will be unavailable from 9:00 PM-midnight ET. We apologize for the inconvenience.
Notice: There is currently an issue with the citation download feature. Learn more.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Apr 1993

Filter Results

Displaying Results 1 - 9 of 9
  • Test generation to minimize error masking

    Publication Year: 1993, Page(s):540 - 549
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    A unified scheme for test-pattern generation and output compaction using circuit-specific information is presented. It is shown that partial control over test-pattern sequence can give zero aliasing in single-output circuits and reduced aliasing in multiple-output circuits. The exact aliasing probability is obtained for multiple-output circuits under the independent bit error model for any test le... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test responses compaction in accumulators with rotate carry adders

    Publication Year: 1993, Page(s):531 - 539
    Cited by:  Papers (61)  |  Patents (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented. In this scheme an accumulator with an n-bit binary adder is slightly modified such that the quality of compaction defined by the asymptotic coverage drop is similar to that offered by shift registers with irreducible polynomials of cellular automata. A Markov-chain model is used to analyze... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Empirical model of MOSFET breakdown voltages

    Publication Year: 1993, Page(s):511 - 515
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    An additive model of drain-to-source current of a MOS transistor in the breakdown region is presented for the circuit-simulation SPICE program. An additional drain-to-source current is described by mixed quadratic and exponential formulas. Continuity of current and its first derivatives is assured. This guarantees a convergence of the Newton-Raphson algorithm used in SPICE. Variation of the drain-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Restructuring and logic minimization for testable PLA

    Publication Year: 1993, Page(s):488 - 496
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    The untestability cube-number product (UCP), a testability measure that can accurately indicate the extra logic needed in testable programmable logic arrays (PLAs), is discussed. Two UCP-based PLA synthesis algorithms are developed. The first one is a restructuring algorithm named REST, and the other is a logic minimizer for testable PLA named LMTPLA. REST can make the restructured PLA testable by... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A beta model for estimating the testability and coverage distributions of a VLSI circuit

    Publication Year: 1993, Page(s):550 - 554
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A relation between fault coverage and testability is employed to predict population coverage. The testability profile is modeled as a mixture of a discrete impulse function and a continuous beta distribution. The parameters of the modeled distribution are estimated from fault coverage data obtained on a sample of faults. The beta distribution is chosen due to its flexible nature. The computed valu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Switch-level timing simulation of bipolar ECL circuits

    Publication Year: 1993, Page(s):516 - 530
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1204 KB)

    A method for switch-level timing simulation of bipolar emitter-coupled-logic (ECL) circuits is presented. The approach is based on the development of a switch level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and the symbolic logic expressions, which represent the logic states of the nodes in terms of subcircuit i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Clock period minimization with wave pipelining

    Publication Year: 1993, Page(s):461 - 472
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constraint-based channel routing for analog and mixed analog/digital circuits

    Publication Year: 1993, Page(s):497 - 510
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB)

    A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges, and increasing the weights of edges in the VC graph in order to meet crossover constraints between orthogonal segments and adjacency constraints be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automating the design of computer systems

    Publication Year: 1993, Page(s):473 - 487
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1376 KB)

    A hierarchical select-and-interconnect methodology for system-level design is described. It extends the flexibility of previous approaches by allowing dynamic subproblem ordering, which is essential for this domain. The design model of M1, a knowledge-based system that implements this approach for small computer systems, is presented. M1's design space covers five microprocessor families, and it h... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu