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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 1993

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Displaying Results 1 - 12 of 12
  • Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy

    Page(s): 537 - 547
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB)  

    The chip design for a fast Fourier transform (FFT) butterfly module using a novel concurrent error detection (CED) technique is presented. It is a time-redundant realization based on the direct complex computation approach. By the use of symmetry and the exchanging design strategy, the recomputation step can be performed by interleaving the circuits for the real and imaginary parts in a complex function. It leads to a lower hardware overhead (about 7/(4n+8), where n is the word length), and the error detection capability is as robust as that of the duplicated module technique. The CED butterfly is designed in 1.2-μm CMOS technology, using the structural silicon complier. The theoretical analysis and experimental results are presented. It is shown that the design is very attractive for real-time high-reliability DSP systems. Its regular structure make the proposed algorithm and architecture easy to implement in VLSI or WSI View full abstract»

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  • 70-MHz 2-μm CMOS bit-level systolic array median filter

    Page(s): 530 - 536
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-μm CMOS technology have been successfully tested at a clock frequency over 70 MHz View full abstract»

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  • Non-quasi-static effects in advanced high-speed bipolar circuits

    Page(s): 613 - 617
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    A detailed study on the non-quasi-state (NQS) effects in advanced high-speed bipolar circuits is presented. An NQS Gummel-Poon-compatible lumped circuit model, which accounts for carrier propagation delays across various quasi-neutral regions in bipolar devices, is implemented in the ASTAP circuit simulator. The effects are then evaluated and compared with those for the conventional Gummel-Poon model for the emitter-coupled logic (ECL) circuit, the non-threshold-logic (NTL) circuit, and various advanced circuits utilizing active-pull-down schemes. For the ECL circuit, the effect decreases with reduced power level and increased loading. For the NTL circuit, due to its front-end configuration, the effect is more significant than that for the ECL circuit but tends to increase with reduced power level. As the passive resistors (and the associated parasitic RC effect) are decoupled from the delay path and the circuit delay is made more intimately related to the intrinsic speed of the devices in various advanced active-pull-down circuits, the delay degradation due to NQS effect becomes more significant View full abstract»

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  • A CMOS analog-digital audio processor for a portable radiotelephone

    Page(s): 560 - 568
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    A mixed analog-digital (A/D) integrated circuit (IC) specifically designed to realize the audio processing functions needed for a portable radiotelephone (PRT) application is described. Multirate signal processing techniques are used to reduce the capacitance spread, and hence the overall silicon area, of the chip, as well as to minimize the settling requirements of the amplifiers for lower power consumption. This, together with programmable power-saving control circuitry also incorporated on-chip, considerably extends the lifetime of the battery. A semicustom design methodology is employed to implement such an application-specific integrated circuit (ASIC) in a 3-μm CMOS double-poly processing technology. Experimental results are presented to demonstrate the correct operation and functionality of the prototype chips View full abstract»

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  • Delta-sigma modulation in fractional-N frequency synthesis

    Page(s): 553 - 559
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A description is given of a delta-sigma (Δ-Σ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Δ-Σ modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional- N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques View full abstract»

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  • Modeling and simulation of hot-carrier-induced device degradation in MOS circuits

    Page(s): 585 - 595
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    The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions View full abstract»

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  • A transistor-only low-pass filter with adjustable bias and small phase shift at high frequencies

    Page(s): 610 - 612
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    A third-order, low-pass, transistor-only filter with a small phase shift at high frequency and an adjustable cutoff frequency is presented. This low-pass filter overcomes the structure limit of the filter previously reported and achieves the same frequency response. It has an adjustable bias voltage which makes it possible to change its cutoff frequency View full abstract»

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  • Power partition and emitter size optimization for bipolar ECL circuit

    Page(s): 548 - 552
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    An automated approach for optimizing the performance of a bipolar ECL circuit is described. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and emitter-follower stages. During the iteration of the optimization process, the optimum obtained from each approximate surface is used as the nominal point for the next iteration. As the nominal point converges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for high-performance ECL circuits are also discussed View full abstract»

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  • Fully balanced CMOS current-mode circuits

    Page(s): 569 - 575
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    A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with Vdd 5 V View full abstract»

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  • Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction

    Page(s): 596 - 604
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    Analytical models for self-aligned-gate AlGaAs/GaAs MODFET's that predict static current-voltage characteristics continuously from below to above threshold are presented. The characteristic equations are derived from fundamental device analysis and contain no nonphysical fitting parameters. They are closed-form and describe device behavior explicitly in terms of terminal voltages. The model equations are amenable to modification for incorporating short-channel effects both in the subthreshold and above-threshold operating regimes. Comparisons of model predictions with data from numerical models are presented. In addition to retaining the physical basis of MODFET operation, the models, due to their relative simplicity, promise digital circuit design, analysis, and simulations with accuracy, ease, and efficiency View full abstract»

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  • A high-precision VLSI winner-take-all circuit for self-organizing neural networks

    Page(s): 576 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB)  

    The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2-μm CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks View full abstract»

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  • A CMOS fully integrated antilarsen system for digital telephones

    Page(s): 605 - 609
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    An integrated CMOS antilarson system that requires no external components is presented. Speech time constants as long as 100 ms are digitally realized. A 12-dB antilarsen depth and a 6-dB hysteresis are provided for the specific application where the system is involved, but both of them and the voice time constants can be register programmed to different values. The extra area added to the chip for the antilarsen function is only 0.5 mm2 in a 1.5-μm CMOS technology View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan