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IEEE Computer Architecture Letters

Issue 1 • Date Jan.-June 2011

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Displaying Results 1 - 13 of 13
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • Cover 2

    Publication Year: 2011, Page(s): c2
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  • Editorial: Letter from the Editor-in-Chief

    Publication Year: 2011, Page(s):1 - 3
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  • Fairness Metrics for Multi-Threaded Processors

    Publication Year: 2011, Page(s):4 - 7
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    Multi-threaded processors execute multiple threads concurrently in order to increase overall throughput. It is well documented that multi-threading affects per-thread performance but, more importantly, some threads are affected more than others. This is especially troublesome for multi-programmed workloads. Fairness metrics measure whether all threads are affected equally. However defining equal t... View full abstract»

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  • Prefetching in Embedded Mobile Systems Can Be Energy-Efficient

    Publication Year: 2011, Page(s):8 - 11
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (545 KB) | HTML iconHTML

    Data prefetching has been a successful technique in high-performance computing platforms. However, the conventional wisdom is that they significantly increase energy consumption, and thus not suitable for embedded mobile systems. On the other hand, as modern mobile applications pose an increasing demand for high performance, it becomes essential to implement high-performance techniques, such as pr... View full abstract»

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  • Papers 
  • DCC: A Dependable Cache Coherence Multicore Architecture

    Publication Year: 2011, Page(s):12 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB) | HTML iconHTML

    Cache coherence lies at the core of functionally-correct operation of shared memory multicores. Traditional directory-based hardware coherence protocols scale to large core counts, but they incorporate complex logic and directories to track coherence states. Technology scaling has reached miniaturization levels where manufacturing imperfections, device unreliability and occurrence of hard errors p... View full abstract»

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  • DRAMSim2: A Cycle Accurate Memory System Simulator

    Publication Year: 2011, Page(s):16 - 19
    Cited by:  Papers (134)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (506 KB) | HTML iconHTML

    In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the c... View full abstract»

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  • Exploiting SPMD Horizontal Locality

    Publication Year: 2011, Page(s):20 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    In this paper, we analyze a particular spatial locality case (called horizontal locality) inherent to manycore accelerator architectures employing barrel execution of SPMD kernels, such as GPUs. We then propose an adaptive memory access granularity framework to exploit and enforce the horizontal locality in order to reduce the interferences among accelerator cores memory accesses and hence improve... View full abstract»

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  • GCMS: A Global Contention Management Scheme in Hardware Transactional Memory

    Publication Year: 2011, Page(s):24 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (525 KB) | HTML iconHTML

    Hardware Transactional Memory (HTM) is a promising Transactional Memory (TM) implementation because of its strong atomicity and high performance. Unfortunately, most contention management approaches in HTMs are dedicated to specific transaction conflict scenarios and it is hard to choose a universal strategy for different workloads. In addition, HTM performance degrades sharply when there are seve... View full abstract»

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  • 2010 Reviewers List

    Publication Year: 2011, Page(s): 28
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  • 2010 Annual Index

    Publication Year: 2011
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  • Cover 3

    Publication Year: 2011, Page(s): c3
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  • Cover 4

    Publication Year: 2011, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

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Meet Our Editors

Editor-in-Chief
José Martinez
Cornell University
336 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
e-mail: martinez@cornell.edu