By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • July 2011

Filter Results

Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2011, Page(s): C1
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2011, Page(s): C2
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • Error Tolerance in Server Class Processors

    Publication Year: 2011, Page(s):945 - 959
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (781 KB) | HTML iconHTML

    This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of promise, based on published literature; and 4)... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators

    Publication Year: 2011, Page(s):960 - 971
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    The probe-based harmonic balance (HB) method is a well-known and largely used tool to compute the steady state behavior of autonomous circuits (oscillators). In this paper, the method is extended to analyze coupled oscillators, where the working frequencies and conditions, i.e., pulling and locking modes, have great relevance. It is shown that probe insertion can be considered as a specific matrix... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On Phase Models for Oscillators

    Publication Year: 2011, Page(s):972 - 985
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (679 KB) | HTML iconHTML

    Oscillators have been a research focus for decades in many disciplines such as electronics and biology. The time keeping capability of oscillators is best described by the scalar quantity phase. Phase computations and equations describing phase dynamics have been useful in understanding oscillator behavior and designing oscillators least affected by disturbances such as noise. In this paper, we pr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips

    Publication Year: 2011, Page(s):986 - 999
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (895 KB) | HTML iconHTML

    Recent advances in digital microfluidics have enabled lab-on-a-chip devices for DNA sequencing, immunoassays, clinical chemistry, and protein crystallization. Basic operations such as droplet dispensing, mixing, dilution, localized heating, and incubation can be carried out using a 2-D array of electrodes and nanoliter volumes of liquid. The number of independent input pins used to control the ele... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Placement and Routing for Cross-Referencing Digital Microfluidic Biochips

    Publication Year: 2011, Page(s):1000 - 1010
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (350 KB) | HTML iconHTML

    Computer-aided design problems of digital microfluidic biochips are receiving much attention, and most of the previous works focus on direct-addressing biochips. In this paper, we solve the placement and droplet routing problem in cross-referencing biochips. In these biochips, the electrodes are addressed in a row-column manner, which may cause electrode interference that prevents simultaneous mov... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts

    Publication Year: 2011, Page(s):1011 - 1019
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB) | HTML iconHTML

    As integrated circuit technologies are scaled down to the nanometer regime, process variations have increasing impact on circuit timing. To address this issue, parameterized statistical static timing analysis (SSTA) has been recently developed. In parameterized SSTA, process variations are represented as random variables (RVs) and timing quantities (delays and others) are expressed as functions of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement

    Publication Year: 2011, Page(s):1020 - 1033
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (470 KB) | HTML iconHTML

    This paper presents a completely new approach to the problem of hypergraph clustering for wirelength-driven placement. The novel algorithm we propose is called SafeChoice (SC). Different from all previous approaches, SC is proposed based on a fundamental theorem, safe condition which guarantees that clustering would not degrade the placement wirelength. To mathematically derive such a theorem, we ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules

    Publication Year: 2011, Page(s):1034 - 1044
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB) | HTML iconHTML

    Fixed outline floorplanning has recently attracted more attention due to its usefulness in solving real problems in industry. This paper applies two convex optimization methods, named UFO, to solve this problem, which consists of a global distribution stage followed by a local legalization phase. In the first stage, modules are transformed into circles, and a push-pull (PP) model is proposed to un... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

    Publication Year: 2011, Page(s):1045 - 1057
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1089 KB) | HTML iconHTML

    In this paper, we present an effective and efficient framework to minimize clock latency range (CLR), which is a crucial objective measuring the process variability of the high-performance clock network. An enhanced deferred-merge embedding algorithm is proposed to handle the skew and slew constraints simultaneously. Besides, instead of using traditional buffering methods that consider only capaci... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • METER: Measuring Test Effectiveness Regionally

    Publication Year: 2011, Page(s):1058 - 1071
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (765 KB) | HTML iconHTML

    Researchers from both academia and industry continually propose new fault models and test metrics for coping with the ever-changing failure mechanisms exhibited by scaling fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is vitally important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. E... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • BIST-Based Fault Diagnosis for Read-Only Memories

    Publication Year: 2011, Page(s):1072 - 1085
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (821 KB) | HTML iconHTML

    This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2011, Page(s): 1086
    Request permission for commercial reuse | PDF file iconPDF (225 KB)
    Freely Available from IEEE
  • IEEE copyright form

    Publication Year: 2011, Page(s):1087 - 1088
    Request permission for commercial reuse | PDF file iconPDF (1065 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2011, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (34 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2011, Page(s): C4
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu