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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug 1993

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Displaying Results 1 - 25 of 34
  • Calculation of beam loading using the induced-current method in passive cavities

    Page(s): 1543 - 1548
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    A method for calculating the loaded Q and beam detuning of a passive (gain or idler) cavity in an electron device is presented. It is based on the determination of induced current by a technique often referred to as Ramo's theorem. The induced current is used in conjunction with a lumped equivalent circuit representing the cavity. This leads to a solution for the self-consistent cavity fields. Although the induced-current expression is usually developed from low-frequency models, it is shown that Ramo's theorem is valid for high-frequency, steady-state analysis when the unloaded passive cavity Q is high. The method is used to calculate the loaded Q of the passive cavity of a new type of gyro-resonant electron device, the magnicon View full abstract»

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  • Characteristics of bilateral MOS-controlled thyristors (BMCT)

    Page(s): 1523 - 1529
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    The operation of the continuous-gate-control BMCT and the interrupted-gate-control BMCT is described and compared. Particular attention is focused on the analysis of the turn-on and turn-off characteristics. The result provides useful guidelines for designing these devices. Parameters such as the minimum MOS gate voltages required for turn-on and turn-off and the maximum controllable current are analytically derived and experimentally verified. Switching tests using fabricated devices indicate that BMCT is capable of handling current exceeding 800 A/cm2 with a turn-off time less than 1 μs for discrete devices View full abstract»

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  • Collector-assisted operation of micromachined field-emitter triodes

    Page(s): 1537 - 1542
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    The field at the tip of a field emitter triode can be expressed by EVg+γV c, where Vg and Vc the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γVc<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I-Vc curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-Vc and transconductance gm-Vg curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly View full abstract»

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  • High-field breakdown in thin oxides grown in N2O ambient

    Page(s): 1437 - 1445
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    A detailed study of time-dependent dielectric breakdown (TDDB) in N2O-grown thin (47-120 Å) silicon oxides is reported. A significant degradation in breakdown properties was observed with increasing oxide growth temperatures. A physical model based on undulations at the Si/SiO2 interface is proposed to account for the degradation. Accelerated breakdown for higher operating temperatures and higher oxide fields as well as thickness dependence of TDDB are studied under both polarities of injection. Breakdown under unipolar and bipolar stress in N2O oxides is compared with DC breakdown. An asymmetric improvement in time-to-breakdown under positive versus negative gate unipolar stress is observed and attributed to charge detrapping behavior in N2O oxides. A large reduction in time-to-breakdown is observed under bipolar stress when the thickness is scaled below 60 Å. A physical model is suggested to explain this behavior. Overall, N2O oxides show improved breakdown properties compared with pure SiO2 View full abstract»

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  • Investigation of the impact ionization in the hydrodynamic model

    Page(s): 1501 - 1507
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    The effects of impact ionization are studied in the framework of a standard hydrodynamic model. Three prescriptions of impact ionization are implemented in the device simulator HFIELDS. They are: (1) a model of Scholl and Quade developed from the Boltzmann transport equation; (2) an empirical model of Baccarani and Stork; and (3) a postprocessor method. Three thin-base Si bipolar devices are simulated. The numerical results show that over a certain range of electric field, the multiplication factors simulated from the Scholl-Quade model, and the Baccarani-Stork model agree very well with the experiment. At very high fields, these models tend to underestimate the net generation rate. Invoking the postprocessor technique, good agreement is found between simulation and experiment. However, at high fields the postprocessor method can lead to erroneous base and collector currents. The limitations of the Scholl-Quade model and how it can be extended for high-field applications are considered View full abstract»

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  • Emission characteristics of silicon vacuum triodes with four different gate geometries

    Page(s): 1530 - 1536
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    Arrays of 10×10, 30×30, and 50×50 phosphorus-doped 0.005-0.025 Ω-cm, monocrystalline silicon field emitters have been fabricated with an emitter height of approximately 4.5 μm, a cone angle of 110°, and four gate openings ranging from 1.8 to 5.3 μm. The placement of the rims of the gates range from coplanar with the apexes of the emitters for the 1.8-μm devices to fully recessed for the 5.3-μm devices. The devices have been characterized in terms of geometry-dependent β factors, scaling of emission currents with array size, temperature dependency from room temperature to 48 K, pressure dependency from 2.5×10-9 to 0.8×10-5 torr, current fluctuations at room temperature and at 48 K, and image formation. All of the measurements have been performed by operating the devices in the gate-induced field emission mode View full abstract»

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  • Radiation hardness of MOSFETs with N2O-nitrided gate oxides

    Page(s): 1565 - 1567
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    Radiation hardness of furnace N2O-nitrided gate oxides was investigated for both n- and p-channel MOSFETs by exposing devices in an X-ray radiation system. An enhanced degradation was observed in both control and N2O-nitrided MOSFETs with reduction in the channel length. Compared to MOSFETs with control oxides, N2O-nitrided MOSFETs show an enhanced radiation hardness against positive charge buildup and interface state generation. The effects of channel hot carriers on the irradiated devices with subsequent low-temperature forming gas annealing were also studied. The results show that N2O-nitrided oxides have a greatly enhanced resistance against radiation-induced neutral electron trap generation View full abstract»

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  • A simple two-dimensional model for subthreshold channel-length modulation in short-channel MOSFETs

    Page(s): 1560 - 1563
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    A physical yet simple model that describes subthreshold channel-length modulation and its complex relationship with drain-induced barrier lowering (DIB) in short-channel MOSFETs is derived. The underlying quasi-two-dimensional analysis produced a V DS-independent value for the modulated channel length in weak inversion, which can be used to simplify and correct subthreshold current simulation. The model, supported by numerical device simulation, further gives insight regarding how channel-length modulation scales with structural parameters View full abstract»

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  • Gate current in AlInAs/GaInAs heterostructure insulated-gate field-effect transistors (HIGFETs)

    Page(s): 1358 - 1363
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    A self-aligned WSi gate heterostructure insulated-gate field-effect transistor (HIGFET) with a gate length of 1 μm was fabricated using an AlInAs/GaInAs heterostructure grown by atmospheric pressure metal-organic chemical vapor deposition (MOCVD). The gate current is investigated experimentally and theoretically. The measured gate current was found to be about two orders of magnitude higher than predicted by theory. The origin of this increase is unclear. However, the theoretical result suggests the possibility of reducing the gate current in AlInAs/GaInAs HIGFETs View full abstract»

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  • Multiterminal light-emitting logic device electrically reprogrammable between OR and NAND functions

    Page(s): 1371 - 1377
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    A monolithic multiterminal logic device that functions both optically and electrically as an ORNAND gate, is demonstrated for the first time. The device, based on the real-space transfer of hot electrons into a complementary collector layer, has been implemented in an InGaAs/InAlAs/InGaAs heterostructure grown by molecular beam epitaxy. Excellent performance is obtained at room temperature. The collector current and the optical output power both exhibit the OR and the NAND functions of any two of the three input terminals, these functions being interchangeable by the voltage on the third terminal View full abstract»

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  • Impact of reactive ion etching using O2+CHF3 plasma on the endurance performance of FLOTOX EEPROM cells

    Page(s): 1549 - 1551
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    The influence of the reactive ion etching (RIE) process step performed with O2+CHF3 plasma on the endurance performance of FLOTOX EEPROM cells is investigated. The comparison with the standard wet etching procedure (WEP) shows that the observed higher programming window degradation ΔWp as well as the unbalanced high-to-low state threshold-voltage shifts can be quantitatively attributed to the fluorine (F) contamination of the tunnel oxide layer near the floating gate (FG) electrode View full abstract»

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  • Electromigration reliability of tungsten and aluminum vias and improvements under AC current stress

    Page(s): 1398 - 1405
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    The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model View full abstract»

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  • Geometric factor for Hall mobility characterization using the van der Pauw dual configuration

    Page(s): 1508 - 1511
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    A geometric factor applicable to a wide range of device geometries of the van der Pauw dual configuration is presented. Such a configuration allows a direct retrieval of the Hall mobility in a single measurement of the magnetic-field-induced imbalance in output current. In view of scaling considerations, the geometric factor is characterized simply in terms of device aspect ratio (L/W) and relative electrode separation (d/W). The geometric factor, which is based on numerical computations, overcomes the limitations inherent in the existing form that has been analytically obtained for an infinitesimally small electrode separation. Hence, it is now possible to design practical device geometries which readily lend themselves to in situ measurement and characterization of the material or process in question, without being constrained by photolithography limitations View full abstract»

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  • Coherent transistor

    Page(s): 1512 - 1522
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    The high-frequency operation of an abrupt-heterojunction transistor with ballistic transport in the base is considered. The coherent regime arises at temperatures low enough compared to the injection energy that the injected minority carriers form a nearly collimated and monoenergetic beam. The coherent transistor can have both current gain and power gain at frequencies far above the conventional cutoff. The extended frequency of an intrinsic transistor is limited by the dispersion in the minority-carrier times of flight across the base, rather than the average time of flight itself. The unilateral gain U calculated for an exemplary heterostructure, including the parasitics, demonstrates an active behavior of the coherent transistor in extended frequency ranges View full abstract»

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  • Current transport mechanism in GaInP/GaAs heterojunction bipolar transistors

    Page(s): 1378 - 1383
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    GaInP/GaAs heterojunction bipolar transistors (HBTs) and both graded and abrupt AlGaAs/GaAs HBTs were fabricated. A total of 20 wafers were analyzed. Comparisons of the experimental results establish that the dominant carrier transport mechanism in GaInP/GaAs HBTs is the carrier diffusion through the base layer. This suggests that the conduction-band barrier across the GaInP/GaAs emitter-base junction is so small that the barrier spike does not affect the carrier transport. This result differs from other published results which, by studying device structures other than HBTs, determined the conduction band barrier to be as large as ~50% of the bandgap difference. The findings of the present investigation, however, agree well with another published work which also examined an HBT structure. The difference between these works is discussed View full abstract»

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  • A practical high-latchup immunity design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs

    Page(s): 1432 - 1436
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    A practical high-latchup-immunity design methodology is proposed for high-density internal circuits in standard cell-based CMOS/BiCMOS LSIs. Both locally injected trigger current and uniformly generated trigger current were measured using a new test structure. Focusing on the difference in the well shunt resistance between local and uniform trigger currents, a practical latchup-free guideline based on an analytical model for uniformly generated trigger current in the well is presented for the periodic placement of well contacts dependent on parasitic device parameters, on generated trigger current level, and a layout pattern size View full abstract»

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  • Modeling of electron-hole scattering in semiconductor devices

    Page(s): 1496 - 1500
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    It is generally assumed in device modeling that the effects of electron-hole scattering can be fully accounted for by a suitable reduction in the electron and hole mobilities with injection level, without modifying the semiconductor device equations themselves. Physical considerations indicate that this is not the case, and that electron-hole collisions introduce a direct coupling between the electron and hole currents. This is determined from first principles, and the results of a Boltzmann calculation are described. The key result is that the impact of an electron-hole scattering event depends on the relative drift velocity between electrons and holes. In low injection, the effective minority-carrier diffusion mobility cannot be assumed to be identical to majority-carrier mobilities or to minority-carrier drift mobilities. In high injection, a reduction in the conductivity mobility does not imply a reduction in the ambipolar diffusion constant. Results for p-i-n diodes are given View full abstract»

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  • A 7-mask CMOS process with selective oxide deposition

    Page(s): 1455 - 1460
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    A seven mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist is described. The process modules for self-aligned well and one-mask LDD formation are developed. The features of the process are: (1) short TAT (7 masks to first metallization), (2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and (3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFETs giving a 10% larger on-current for p-channel MOSFETs compared to a conventional process View full abstract»

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  • A new drain-current injection technique for the measurement of off-state breakdown voltage in FETs

    Page(s): 1558 - 1560
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    A simple three-terminal technique for measuring the off-state breakdown voltage of FETs is presented. With the source grounded, current is injected into the drain of the on-state device. The gate is then ramped down to shut the device off. In this process, the drain-source voltage rises to a peak and then drops. This peak represents an unambiguous definition of three-terminal breakdown voltage. In the same scan, a measurement of the two-terminal gate-drain breakdown voltage is also obtained. The method offers potential for use in a manufacturing environment, as it is fully automatable. It also enables easy measurement of breakdown voltage in unstable and fragile devices View full abstract»

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  • Observation of resonant tunneling at room temperature in GaInP/GaAs/GaInP double-heterojunction bipolar transistor

    Page(s): 1384 - 1389
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    Negative differential resistance (NDR) has been observed at room temperature in GaInP/GaAs double-heterojunction bipolar transistors (DHBTs). Both the common-emitter and common-base current-voltage characteristics and their magnetic field dependence have been studied to confirm that the observed NDR is due to resonant tunneling. The collector-base voltages at which the collector current resonances occur are calculated and are consistent with the measured values. The devices exhibit an offset voltage of 57 mV and saturation voltage of ⩽ 2-V, both of which are the lowest reported values for GaInP/GaAs DHBTs. The collector-base breakdown voltage in these DHBTs is 31 V, and its variation with junction temperature is measured and described View full abstract»

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  • Collector design tradeoffs for low voltage applications of advanced bipolar transistors

    Page(s): 1478 - 1483
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    The values of BVceo are computed for transistors with highly doped collectors and with thin reach-through collectors, using various sets of ionization coefficients including new data. Computed values of BVceo are compared with experimental results. It is shown that transistors with thin reach-through collectors have higher current capability for any given BVceo compared to those with highly doped collectors. Tradeoffs in terms of BVceo, maximum collector current and the maximum frequency of operation are studied for transistors with highly doped and thin reach-through collectors View full abstract»

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  • Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2 -implanted base with rapid thermal process

    Page(s): 1484 - 1495
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    Process and device parameters are characterized in detail for a 30-GHz fT submicrometer double poly-Si bipolar technology using a BF2-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10-7 Ω-cm2, while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors View full abstract»

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  • An improved hydrodynamic transport model for silicon

    Page(s): 1469 - 1477
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    A closed set of hydrodynamic equations for silicon device analysis is obtained with the aid of self-consistent Monte Carlo device simulation data. This set of macroscopic equations is derived without invoking any phenomenological relations such as the Fourier law for heat flow and the Wiedemann-Franz law for thermal conductivity. The model is developed by taking the first four moments of the Boltzmann transport equation (BTE). This model taken into account the difference between the moments of the collision terms of the BTE both for bulk and inhomogeneous systems. The cause of the spurious velocity overshoot sometimes predicted by other models is identified. By introducing different levels of approximation, this system of hydrodynamic equations can be reduced to the conventional hydrodynamic or energy transport equations. The improved model appears to be more accurate than any existing approach for modeling silicon devices View full abstract»

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  • A 64-GHz fT and 3.6-V BVCEO Si bipolar transistor using in situ phosphorus-doped and large-grained polysilicon emitter contacts

    Page(s): 1563 - 1565
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    A high-performance bipolar transistor has been developed using an in-situ phosphorus doped polysilicon (IDP) technique for emitter formation. The transistor demonstrated in ultrahigh current gain of 700, a maximum cutoff frequency fT(max) of 64 GHz, and a breakdown voltage between collector and emitter BVCEO of 3.6 V. At VCE values of 2 and 3 V, a product of fT(max) and BVCEO of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors View full abstract»

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  • A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices: a solar cell application

    Page(s): 1446 - 1454
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    As an application of the authors previous model for MIS (metal-insulator-semiconductor) devices, a detailed model for MIS solar cells has been developed that covers a wide range of parameters, including surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function. It also takes the nonequilibrium conditions into consideration. The effects of using the actual permittivity and barrier height of thin oxide are discussed View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology