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Solid-State Circuits, IEEE Journal of

Issue 7 • Date Jul 1993

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Displaying Results 1 - 25 of 27
  • A novel SFG structure for C-T high-pass filters

    Publication Year: 1993 , Page(s): 840 - 844
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A signal flow graph (SFG) structure for simulating passive high-pass ladder filters, called the incremental integration structure, is proposed. The structure requires the use of integrators with nonintegrating inputs, and an implementation based on the MOSFET-C technique is discussed. The incremental integration structure is compared to the leapfrog and direct SFG simulation structures. Leapfrog high-pass filters are relatively simple and show good noise properties, but they are based on differentiators and thus stability problems exist. The direct SFG simulation method is based on integrators and has good stability properties, but it leads to a relatively high circuit complexity and a high noise level. However, the incremental integration structure inherits the low-noise properties of the leapfrog structure and the good stability of the direct SFG simulation method. A sixth-order elliptic high-pass filter chip with a passband frequency of 3.0 kHz has been manufactured, and measurements support the validity of the approach View full abstract»

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  • Analog CMOS realization of fuzzy logic membership functions

    Publication Year: 1993 , Page(s): 857 - 861
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The design of a monolithic CMOS analog function synthesizer based on a current-mode algorithm and its application in fuzzy membership function synthesis is presented. The proposed circuits require only one reference current, independently of the course or the number of implemented functions. The networks are temperature and technology insensitive. Other features are a small chip area and a simple design process for any arbitrary functions. Matching considerations allow a prediction of the available approximation accuracy. Theoretical evaluations are validated by measurements of several membership functions fabricated in an experimental 1.0-μm CMOS technology View full abstract»

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  • Video CMOS power buffer with extended linearity

    Publication Year: 1993 , Page(s): 845 - 848
    Cited by:  Papers (7)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A CMOS power buffer suitable for video applications is discussed. The use of a high-speed push-pull output stage and a highly linear high-speed driver allows good linearity to be maintained even with very high input frequencies. Indeed, total harmonic distortions (THDs) as good as -66 and -58 dB are achieved at 0.5 and 1 MHz, respectively, with a load resistance of 75 Ω. The integrated prototype, realized using a 1.2-μm CMOS process, occupies a silicon area of 280 mils2 View full abstract»

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  • A 40×40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system

    Publication Year: 1993 , Page(s): 799 - 807
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB)  

    An analog VLSI processor chip with application in a high-speed binocular stereo vision system used for the recovery of scene depth is presented. The authors have attempted to exploit the principal advantages of analog VLSI, namely, its small area, high speed, and low power, while minimizing the effects of its limited accuracy, inflexibility, and lack of storage capacity. A CCD/CMOS stereo system implementation, capable of processing several thousand image frame pairs per second for 40×40-pixel binocular images, is proposed. A 40×40-pixel absolute-value-of-difference (AVD) array, a core processor of the stereo system, was fabricated in a 2-μm CCD/CMOS process. Individual unit cells in the array were characterized and tested. The array functionality was tested by imbedding it in a computerized stereo system and using both real-scene and computer-generated input image pairs. The system output is compared with full computer simulations for the same image pairs, showing good correlation View full abstract»

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  • Testable switched-capacitor filters

    Publication Year: 1993 , Page(s): 719 - 724
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach View full abstract»

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  • Wide-band integrated optical receiver with improved dynamic range using a current switch at the input

    Publication Year: 1993 , Page(s): 862 - 864
    Cited by:  Papers (11)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    The front end of optical transmission systems usually consists of a low-noise, wide-band, negative-feedback transimpedance or current amplifier. The dynamic range of current amplifiers can be extended considerably by passing large input currents directly to the output of the amplifier. It is shown that the required current switch does not deteriorate the sensitivity of the receiver. A complete front end, using an external p-i-n photodiode, is integrated in a 2.5-GHz bipolar technology. The receiver has a dynamic range (DR) of 73 dB in a bandwidth of 220 MHz and consumes a supply current of 1.5 mA View full abstract»

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  • A CMOS current-mode operational amplifier

    Publication Year: 1993 , Page(s): 849 - 852
    Cited by:  Papers (43)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process View full abstract»

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  • A 622-Mb/s 8×8 ATM switch chip set with shared multibuffer architecture

    Publication Year: 1993 , Page(s): 808 - 815
    Cited by:  Papers (25)  |  Patents (76)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing View full abstract»

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  • Quality assurance and upgrade of analog characteristics by fast mismatch analysis option in network analysis environment

    Publication Year: 1993 , Page(s): 865 - 871
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    The usefulness and power of fast mismatch analysis options within the network analysis environment are demonstrated. Simulated yield statistics and measurements of a fabricated analog application are reported and compared. The physical connections introduced between local and global process variations lead to new procedures for calculating the overall tolerance ranges of the electrical characteristics. The simulation examples illustrate the comfort of the implementation and provide information regarding interconnections between local mismatch effects and circuit design View full abstract»

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  • Integrated continuous-time balanced filters for 16-b DSP interfaces

    Publication Year: 1993 , Page(s): 835 - 839
    Cited by:  Papers (26)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A fully integrated, low-distortion, balanced, continuous-time filter fabricated in 5-V, 1.6-μm CMOS is presented. Active RC structures are used in a leapfrog topology, with time constants set by integrated passive resistors and capacitors. Accurate tuning is achieved by selection of capacitor elements under the control of a new calibrator circuit. With a 2-Vrms differential input and output, the filter achieves -94-dB THD (total harmonic distortion) and 95-dB signal-to-noise ratio. Tuning accuracy is maintained to within ±5% of nominal over the commercial temperature range View full abstract»

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  • A BiCMOS speech circuit with only two external components

    Publication Year: 1993 , Page(s): 770 - 777
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    A telephone chip that performs all the basic functions of a speech circuit using only two external components is reported. Precision filtering based on switched-capacitor (SC) techniques is used to implement on-chip impedance termination, hybrid with sidetone cancellation, and DC characteristics starting from a single 1% external resistor. A new low-drop on-chip voltage supply generator derived from the line using an external storage capacitor is also realized. Better than 33-dB impedance matching and more than 30-dB sidetone cancellation is achieved without any external trimming. The TX linearity is better than 50 dB up to 4.4 Vp-p on the line. The chip has an active area of approximately 2.6 mm2 and draws 1.5 mA of quiescent current View full abstract»

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  • Extension of the common-mode range of bipolar input stages beyond the supply rails of operational amplifiers and comparators

    Publication Year: 1993 , Page(s): 750 - 757
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    When the input voltage of an operational amplifier or comparator with a bipolar input stage exceeds the range of normal operation, the polarity of the output signal reverses and the input bias current increases to excessively large values. Saturation of the input transistors restricts the sensing of differential voltages to a common-mode (CM) range roughly between the positive and the negative supply rails. Input stage configurations that not only provide solutions to prevent the signal reversal and the excessive increase of input bias current, but also provide an extension of the CM range far beyond the supply rails, while the transconductance for differential input voltages remains constant, are described. Integrated implementations of the input stages realized a CM range reaching +15 V at a single supply voltage as low as 1 V, while the input bias current was limited to 6 μA View full abstract»

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  • A stable high-order delta-sigma modulator with an FIR spectrum distributor

    Publication Year: 1993 , Page(s): 730 - 735
    Cited by:  Papers (8)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    A stable high-order delta-sigma modulator topology is presented. The topology can be completely stabilized for arbitrary order by a finite impulse response (FIR) spectrum distribution technique. The stability of the modulator is examined by means of the root locus method. The topology inherently has less sensitivity to component mismatch, and can be realized without any hardware penalty compared to noise-shaping integrators of the same order. The modulator realizes 16-b resolution at 20-kHz bandwidth when a filter order of four and an oversampling ratio of 64 are employed View full abstract»

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  • Analog circuit implementation on CMOS semi-custom arrays

    Publication Year: 1993 , Page(s): 872 - 874
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    Various requirements for implementing analog or mixed analog/digital circuits on semi-custom arrays are discussed in relation to array architecture. Analog circuit techniques applicable to CMOS arrays are described, and performance results are given. An extended array with dedicated analog area and high-voltage output capability is presented View full abstract»

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  • A programmable artificial retina

    Publication Year: 1993 , Page(s): 789 - 798
    Cited by:  Papers (45)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB)  

    An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities is proposed, with versatility provided by programmability. For a pixel memory size of 3 b, the authors demonstrate both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semistatic shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as six global clock signals. The successful design, integration, and test of a 65×76 Boolean retina on a 50-mm2 CMOS 2-μm circuit are described View full abstract»

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  • A 2-μm CMOS fifth-order low-pass continuous-time filter for video-frequency applications

    Publication Year: 1993 , Page(s): 713 - 718
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A fifth-order elliptic low-pass continuous-time filter based on triode transconductors for applications in the video frequency range is presented. Fabricated in a standard 2-μm CMOS technology, the circuit occupies 6 mm2 of silicon area including the automatic tuning circuitry. The filter achieves a 7-MHz cutoff frequency using a parasitic pole compensation scheme. The dynamic range is 40 dB and power consumption is 30 mW for a 5-V supply. A transconductor biasing strategy which allows a continuous tuning range for the cutoff frequency of one decade is presented View full abstract»

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  • Integrated laser-diode voltage driver for 20-Gb/s optical systems using 0.3-μm gate length quantum-well HEMT's

    Publication Year: 1993 , Page(s): 829 - 834
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    An integrated laser-diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs-GaAs quantum-well high electron mobility transistors (QW HEMTs) with gate lengths of 0.3 μm has been developed. Its large signal bandwidth is 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gb/s show an opening similar to that of the input signal. Supporting material is given indicating that the LDVD might operate at bit rates up to 20 Gb/s. The maximum output current is over 90 mA; the maximum modulation voltage of 800 mV corresponds to 40-mA modulation current for a laser diode with 20-Ω dynamic resistance. The power consumption is less than 500 mW View full abstract»

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  • A broad-bandwidth mixed analog/digital integrated circuit for the measurement of complex impedance

    Publication Year: 1993 , Page(s): 764 - 769
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A broad-bandwidth measuring system for complex impedances is presented. The measuring principle, based on synchronous detection, is worked out mathematically. The final circuit is realized as a mixed analog/digital BiCMOS integrated circuit. The output of the IC is a modulated 100-Hz frequency and RS232. The phase accuracy of the system is 0.07° at 20 MHz and is mainly determined by the parameter deviation of transistors that share the same IC. The circuit enables measurement of a capacitance of up to 100 pF with an accuracy of ±1 pF, in parallel with a conductance of up to 100 mS. Apart from the impedance measuring circuit, the IC can process signals from other sensors, such as for temperature or pH. The design criteria for the IC are derived from the primary application in a sensor for water content and ionic concentration measurements in soil or other agricultural substrates View full abstract»

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  • A low-power 8-b 1 3.5-MHz video CMOS ADC for visiophony ISDN applications

    Publication Year: 1993 , Page(s): 725 - 729
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    A half-flash, subranging, 8-b, 13.5-MHz, video ADC (analog-to-digital converter) using overlapped architecture that combines the advantages of both flash and half-flash converters is described. Its conversion rate is that of a flash, without any multiplexing and with a low number of comparators. Its low power consumption and the small silicon area required for its implementation enable it to be integrated in mixed digital/analog circuits such as a video acquisition circuit devoted to visiophony applications. It has been manufactured using a CMOS 1-μm technology with two polysilicon and two metallization layers View full abstract»

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  • A CMOS low-distortion fully differential power amplifier with double nested Miller compensation

    Publication Year: 1993 , Page(s): 758 - 763
    Cited by:  Papers (40)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -Vp-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V p-p output signal, THD is -68 dB. The chip area is 0.625 mm 2 in a 1.5-μm single-poly, double-metal, n-well CMOS technology View full abstract»

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  • Silicon bipolar laser driving IC for 5 Gb/s and 45-mA modulation current and its application in a demonstrator system

    Publication Year: 1993 , Page(s): 824 - 828
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The design and implementation of a 5-Gb/s silicon bipolar laser driver IC for direct modulation of a laser diode is reported. The adjustable modulation current range is 15-45 mA. The IC can drive 25-Ω laser modules via a 25-Ω transmission line. Typical power dissipation is 930 mW for a modulation current of 45 mA. Though the IC has been fabricated on a production line instead of using a laboratory technology, it is one of the fastest laser driver ICs ever implemented in silicon. The ability to drive an ohmic load is shown, as well as the performance when driving a real laser module. The circuit has been successfully operated in a demonstrator system for digital optical-fiber transmission View full abstract»

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  • Analog phase measuring circuit for digital CMOS ICs

    Publication Year: 1993 , Page(s): 853 - 856
    Cited by:  Papers (12)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed View full abstract»

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  • Yield optimization of analog ICs using two-step analytic modeling methods

    Publication Year: 1993 , Page(s): 778 - 783
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    Innovative methods for statistical design optimization have been applied to the development of analog IC blocks. The most important feature of these methods is the derivation of an analytic function representing the yield surface in the design parameter space. Using this analytic model it is possible to optimize the yield accurately and efficiently. All the required operations are implemented in an integrated and fully automated CAD system. A comparison between simulated and measured data for several wafer lots demonstrates the validity of the approach View full abstract»

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  • A nonvolatile analog programmable voltage source using the VIPMOS EEPROM structure

    Publication Year: 1993 , Page(s): 784 - 788
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    A programmable voltage source using the vertical injection punchthrough based MOS (VIPMOS) EEPROM structure is presented. The circuit operates at a single 5-V supply and the output voltage is continuously available even during programming. The effect of programming is linearly dependent on the programming time. During programming no crosstalk from the enable pulses and only a little crosstalk from the program current are observed. If a decreasing program current is used, the output of the circuit can be set to its desired value without the need of an iterative program process View full abstract»

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  • A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays

    Publication Year: 1993 , Page(s): 816 - 823
    Cited by:  Papers (13)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    A high-speed small-area DRAM sense amplifier with a threshold-voltage (VT) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple VT mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in VT mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan