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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 6 • Date June 2011

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  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

    Page(s): 1157 - 1166
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1390 KB) |  | HTML iconHTML  

    A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0-V supply. View full abstract»

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  • A 14 b 23 MS/s 48 mW Resetting \Sigma \Delta ADC

    Page(s): 1167 - 1177
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    High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasingly difficult to design in low-voltage nanometer-scale CMOS processes. We propose an ADC architecture based on a resetting ΣΔ modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a second-order resetting ΣΔ modulator and a 10 b cyclic ADC. The device achieves 14 b resolution and samples as a Nyquist converter at 23 MS/s. This calibration-free ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. The ADC is fabricated in 0.18 μm CMOS and occupies a core area of 0.5 mm2. It consumes 48 mW from a 2 V supply. View full abstract»

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  • The Sampling Theorem With Constant Amplitude Variable Width Pulses

    Page(s): 1178 - 1190
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    This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within ±0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level. The proof of the sampling theorem uses a simple iterative technique that is guaranteed to converge to the exact PWM representation whenever it exists. The paper goes on to develop a practical matrix based iterative technique to generate the PWM waveform that is guaranteed to converge exponentially. The peak constraint in the theorem is only a sufficient condition. In fact, many signals with higher peaks, e.g., lower than Nyquist frequency sinusoids, can be accurately represented by a PWM waveform. View full abstract»

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  • A 5 Gb/s Automatic Within-Pair Skew Compensator for Differential Data in 0.13 \mu{\hbox {m}} CMOS

    Page(s): 1191 - 1202
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    This paper presents an automatic within-pair skew compensator for high-speed differential data transmission. A wide-bandwidth data delay line is proposed to provide adjustable delay for data signals. Also presented is an on-chip within-pair skew detection circuit to detect skew between the differential data signals for automatic close-loop skew compensation. A within-pair skew compensator prototype for 5 Gb/s data was fabricated in 0.13 μm CMOS. Measurement results show that the within-pair skew compensator can automatically compensate for within-pair skew of ± 200 ps (± 1 unit interval). It consumes 20.4 mW from 1.2 V supply and occupies 0.015 mm2 die area. View full abstract»

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  • Positive Linear Systems Consisting of n Subsystems With Different Fractional Orders

    Page(s): 1203 - 1210
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    A new class of positive linear systems consisting of n subsystems with different fractional orders is introduced. Solution to the set of matrix linear differential equations with different fractional orders is derived. Necessary and sufficient conditions for the positivity of the fractional systems are established. It is shown that the linear electrical circuits composed of resistors, supercondensators, coils, and voltage (current) sources are positive systems with different fractional orders. View full abstract»

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  • Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

    Page(s): 1211 - 1224
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    Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL. View full abstract»

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  • A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

    Page(s): 1225 - 1238
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    In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loading for previous RF stages. When compared to CML, they offer low transistor count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a large low-to-high propagation delay, which limits their speed and results in asymmetrical output waveforms. The proposed DCVSL-R circuit embodies the benefits of DCVSL while reducing the total propagation delay, achieving faster operation. DCVSL-R also generates symmetrical output waveforms which are critical for differential circuits. Another contribution of this work is a closed-form delay model that predicts the speed of DCVSL circuits with 8% worst case accuracy. We implement two ring-oscillator-based VCOs in 0.13 μm technology with DCVSL and DCVSL-R delay cells. Measurements show that the proposed DCVSL-R based VCO consumes 30% less power than the DCVSL VCO for the same oscillation frequency (2.4 GHz) and same phase noise (-113 dBc/Hz at 10 MHz). DCVSL-R circuits are also used to implement the high frequency dual modulus prescaler (DMP) of a 2.4 GHz frequency synthesizer in 0.18 μm technology. The DMP consumes only 0.8 mW at 2.48 GHz, a 40% reduction in power when compared to other reported DMPs with similar division ratios and operating frequencies. The RF buffer that drives the DMP consumes only 0.27 mW, demonstrating the lowest combined DMP and buffer power consumption among similar synthesizers in literature. View full abstract»

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  • Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM

    Page(s): 1239 - 1251
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    Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-of-the-art SRAM designs employ replica timing control circuit to mitigate the effects of leakage and process variation, optimize the performance, and reduce power consumption. NBTI and PBTI also degrade the timing control circuits and may render them ineffective. In this paper, we provide comprehensive analyses on the impacts of NBTI and PBTI on a two-port 8T SRAM design, including the stability and Write margin of the cell, Read/Write access paths, and replica timing control circuits. We show, for the first time, that because the Read/Write replica timing control circuits are activated in every Read/Write cycle, they exhibit distinctively different degradation behavior from the normal array access paths, resulting in degradation of timing control and performance. We also discuss degradation tolerant design techniques to mitigate the performance and reliability degradation induced by NBTI/PBTI. View full abstract»

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  • An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

    Page(s): 1252 - 1263
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    Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode. Thus, several 8T and 10T cell designs have been reported, improving the cell stability. However, they either employ single-ended read port or require too large area. In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting Code (ECC). It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. To verify the technique, a 128 × 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the proposed design has 2× higher noise margin and consumes 54% less power when compared to the conventional 6T design. View full abstract»

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  • A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines

    Page(s): 1264 - 1276
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    In this paper, a bus design scheme that achieves both impedance matching and uniform power distribution for a multidrop bus is presented. In contrast to conventional schemes, the proposed scheme lets the line impedance of each segment of the bus vary, and the impedance-matching resistance values are determined accordingly, thereby providing higher degrees of freedom for optimization. General formulas for determining the optimal line impedances and matching resistances are derived. The voltage and power ratios between the master driver and branch receivers are also established, showing that such ratios depend only on the master-to-branch impedance ratio and the number of branches. Similar relations are also derived for the backward direction. The measurement results of the fabricated FR4 printed circuit boards demonstrate good agreement with the theoretical results, and show reliable performance up to a bit rate of 5 Gbps. View full abstract»

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  • A Low-Cost VLSI Architecture for Robust Distributed Estimation in Wireless Sensor Networks

    Page(s): 1277 - 1286
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1954 KB) |  | HTML iconHTML  

    A robust distributed estimation scheme for fusion center in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efficiently and improve the accuracy of the estimates significantly. It achieves very good performance at the expense of such extensive computations as logarithm and division in the detecting process. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device. Therefore, a simple and efficient distributed estimation scheme requiring lower hardware cost and power consumption is extremely desired for fusion center. In this paper, we propose the efficient collaborative sensor fault detection (ECSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The circuit of ECSFD contains 22589 gates and requires a core size of 571 × 559 μm2 by using TSMC 0.18 μm cell library. Simulation results indicate the accuracy of the estimates obtained from the ECSFD is better than that obtained from a conventional approach. View full abstract»

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  • Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images

    Page(s): 1287 - 1299
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    An infiltrative nature on ultrasound images is a significant feature of malignant breast lesion. Characterizing the infiltrative nature with highly efficacious and computationally inexpensive features is crucial for computer-aided diagnosis. The local variance can be characterized by a few high octave energies in the 1-D discrete periodized wavelet transform (DPWT). For the realization of high octave energy extraction, a non-recursive DPWT called 1-D RRO-NRDPWT and a segment accumulation algorithm (SAA) are applied. The 1-D RRO-NRDPWT is used to solve the word-length-growth (WLG) problem existing in high octave decomposition. The SAA is used to overcome the filter-tap-growth (FTG) effect existing in the 1-D NRDPWT. Incorporating these two strategies, a SAA-based VLSI architecture is presented for high octave decomposition. The influence of the finite precision process on feature efficacy is also analyzed for hardware efficiency improvement. Hardware simulation shows that with 7-bit filter coefficient representation, the core size of the octave energy feature (D6E5) extractor is about 335.295*335.295 μm2 where the wavelet transformation will take about 54.87% and 2.875 mW. View full abstract»

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  • Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC

    Page(s): 1300 - 1310
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    This paper introduces an adaptive calibration structure for the blind calibration of frequency response mismatches in a two-channel time-interleaved analog-to-digital converter (TI-ADC). By representing frequency response mismatches as polynomials, we can exploit slight oversampling to estimate the coefficients of the polynomials by using the filtered-X least-mean square (FxLMS) algorithm. Utilizing the coefficients in an adaptive structure, we can compensate frequency response mismatches including time offset and bandwidth mismatches. We develop an analytical framework for the calibration structure and analyze its performance. We show the efficiency of the calibration structure by simulations, where we include examples from the literature. View full abstract»

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  • Efficient Design and Implementation of Variable Fractional Delay Filters Using Differentiators

    Page(s): 1311 - 1322
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    In this paper, the power series expansion of exponential function is used to transform the design problem of variable fractional delay (VFD) filter into the designs of digital differentiators with various orders such that conventional digital differentiators can be applied to implement VFD filter efficiently. The proposed method is flexible because the VFD filter can be designed by making the trade-off among the storage requirement of filter coefficients, computational complexity and delay of filter. Finally, some numerical examples are demonstrated to show the effectiveness and flexibility of the proposed design methods. View full abstract»

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  • Nonlinear Dynamics of Memristor Oscillators

    Page(s): 1323 - 1336
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    A thorough investigation of the nonlinear dynamics of networks of memristor oscillators is a key step towards the design of systems based upon them, such as neuromorphic circuits and dense nonvolatile memories. A wide gamut of complex dynamic behaviors, including chaos, is observed even in a simple network of memristor oscillators, proposed here as a good candidate for the realization of oscillatory associative and dynamic memories. A detailed study of number and stability of all periodic and nonperiodic oscillations appearing in the network may not leave aside a preliminary deep understanding of the local and global behavior of the basic oscillator. Depending on two bifurcation parameters, controlling memristor nonlinearity, the oscillator exhibits different dynamic behaviors, analyzed here through application of state-of-the-art techniques from the theory of nonlinear dynamics to the oscillator model. View full abstract»

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  • Controlling Chaos in a Memristor Based Circuit Using a Twin-T Notch Filter

    Page(s): 1337 - 1344
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    After the successful solid state implementation of memristors, a lot of attention has been drawn to the study of memristor based chaotic circuits. In this paper, a systematic study of chaotic behavior in such system is performed with the help of nonlinear tools such as bifurcation diagrams, power spectrum analysis, and Lyapunov exponents. In particular, a Twin-T notch filter feedback controller is designed and employed to control the chaotic behavior in the memristor based chaotic circuit. Both simulation and experiment results validate the proposed control method. View full abstract»

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  • Lag Quasi-Synchronization of Coupled Delayed Systems With Parameter Mismatch

    Page(s): 1345 - 1357
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    This paper is concerned with lag synchronization of two coupled delayed systems with parameter mismatch. Due to parameter mismatch, complete lag synchronization can not be achieved. Therefore, a new lag quasi-synchronization scheme is proposed to ensure that coupled systems are in a state of lag synchronization with an error level. Several simple criteria are derived and the error level is estimated by applying a generalized Halanary inequality and matrix measure. Three examples are given to illustrate the effectiveness of the proposed lag quasi-synchronization scheme. It is shown that as the coupling strength increases, the estimated error level is close to the simulated one, which well supports theoretical results. View full abstract»

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  • Synchronization in Networks of Diffusively Time-Delay Coupled (Semi-)Passive Systems

    Page(s): 1358 - 1371
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    We consider networks with a general topology which consist of nonlinear systems that interact via diffusive coupling with constant time-delays. Using the notion of (semi-)passivity we prove under some mild assumptions that passive systems will synchronize and that the solutions of interconnected semi-passive systems will be bounded. Furthermore we prove that identical strictly semi-passive systems, whose internal dynamics are stable, always will synchronize given that the coupling between the systems is sufficiently strong and a possible constant time delay is sufficiently small. We demonstrate our results using numerical simulations of a network consisting of linear systems and a network consisting Hindmarsh-Rose neurons. View full abstract»

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  • In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

    Page(s): 1372 - 1381
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2188 KB) |  | HTML iconHTML  

    For anti-fuse or flash-memory-based field-programmable gate arrays (FPGAs), single-event transient (SET)-induced faults are significantly more pronounced than single-event upsets (SEUs). While most existing work studies SEU, this paper proposes a retiming algorithm for mitigating variational SETs (i.e., SETs with different durations and strengths). Considering the reshaping effect of an SET pulse caused by broadening and attenuation during its propagation, SET-aware retiming (SaR) redistributes combinational paths via post layout retiming and minimizes the possibility that an SET pulse is latched. The SaR problem is formulated as an integer linear programming (ILP) problem and solved efficiently by a progressive ILP approach. In contrast to existing SET-mitigation techniques, the proposed SaR does not change the FPGA architecture or the layout of an FPGA application. Instead, it reconfigures the connection between a flip-flop and an LUT within a programmable logic block. Experimental results show that SaR increases mean-time-to-failure (MTTF) by 78% for variational SETs with a 10-min runtime limit while preserving the clock frequency on ISCAS89 benchmark circuits. To the best of our knowledge, this paper is the first in-depth study on FPGA retiming for SET mitigation. View full abstract»

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  • Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis

    Page(s): 1382 - 1395
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2190 KB) |  | HTML iconHTML  

    This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) analog circuits. Nullators and norators along with the voltage mirror-current mirror (VM-CM) pair (collectively known as pathological elements) are used to model the behavior of active devices in voltage-, current-, and mixed-mode, also considering parasitic elements. Since analog circuits are transformed to nullor-based equivalent circuits or VM-CM pairs or as a combination of both, standard nodal analysis can be used to formulate the admittance matrix. We present a formulation method in order to build the nodal admittance (NA) matrix of nullor-equivalent circuits, where the order of the matrix is given by the number of nodes minus the number of nullors. Since pathological elements are used to model the behavior of active devices, we introduce a more efficient formulation method in order to compute small-signal characteristics of pathological element-based equivalent circuits, where the order of the NA matrix is given by the number of nodes minus the number of pathological elements. Examples are discussed in order to illustrate the potential of the proposed pathological element-based active device models and the new formulation method in performing symbolic analysis of analog circuits. The improved formulation method is compared with traditional formulation methods, showing that the NA matrix is more compact and the generation of nonzero coefficients is reduced. As a consequence, the proposed formulation method is the most efficient one reported so far, since the CPU time and memory consumption is reduced when recursive determinant-expansion techniques are used to solve the NA matrix. View full abstract»

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  • Adaptive Synchronization of a Class of Uncertain Complex Networks Against Network Deterioration

    Page(s): 1396 - 1409
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    This paper is concerned with the robust synchronization problem for a class of uncertain dynamical complex networks against network deterioration. As deteriorated networks and uncertainties may lead to performance degradation or even instability of the whole network, an adaptive approach is proposed to adjust unknown coupling factors for the deteriorated network compensations, as well as to estimate controller parameters to compensate the effects of uncertainty on-line without assuming symmetry or irreducibility of networks. Through Lyapunov functions and adaptive schemes, pinning controllers are constructed to ensure that the synchronization errors of the networks can be reduced as small as desired in the presence of the network deterioration and uncertainty. Simulation results are given to verify the effectiveness of the proposed method. View full abstract»

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  • A Counterexample to “ Positive Realness Preserving Model Reduction With {cal H}_{\infty } Norm Error Bounds”

    Page(s): 1410 - 1411
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    We provide a counterexample to the H error bound for the difference of a positive real transfer function and its positive real balanced truncation stated in “Positive realness preserving model reduction with H norm error bounds,” IEEE Trans. Circuits Syst, I, Fundam. Theory Appl., vol. 42, no. 1, pp. 23-29 (1995). The proof of the error bound is based on a lemma from an earlier paper, “A tighter relative-error bound for balanced stochastic truncation,” Syst. Control Lett., vol. 14, no. 4, 307-317 (1990), which we also demonstrate is false by our counterexample. The main result of this paper was already known in the literature to be false. We state a correct H error bound for the difference of a proper positive real transfer function and its positive real balanced truncation and also an error bound in the gap metric. View full abstract»

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  • High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

    Page(s): 1412 - 1420
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    This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-24 SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras