# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2011, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2011, Page(s): C2
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• ### A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

Publication Year: 2011, Page(s):1157 - 1166
Cited by:  Papers (22)
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A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.... View full abstract»

• ### A 14 b 23 MS/s 48 mW Resetting $Sigma Delta$ ADC

Publication Year: 2011, Page(s):1167 - 1177
Cited by:  Papers (10)
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High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasingly difficult to design in low-voltage nanometer-scale CMOS processes. We propose an ADC architecture based on a resetting ΣΔ modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a second-o... View full abstract»

• ### The Sampling Theorem With Constant Amplitude Variable Width Pulses

Publication Year: 2011, Page(s):1178 - 1190
Cited by:  Papers (9)
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This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within ±0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is tw... View full abstract»

• ### A 5 Gb/s Automatic Within-Pair Skew Compensator for Differential Data in 0.13 $mu{hbox{m}}$ CMOS

Publication Year: 2011, Page(s):1191 - 1202
Cited by:  Papers (1)  |  Patents (1)
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This paper presents an automatic within-pair skew compensator for high-speed differential data transmission. A wide-bandwidth data delay line is proposed to provide adjustable delay for data signals. Also presented is an on-chip within-pair skew detection circuit to detect skew between the differential data signals for automatic close-loop skew compensation. A within-pair skew compensator prototyp... View full abstract»

• ### Positive Linear Systems Consisting of $n$ Subsystems With Different Fractional Orders

Publication Year: 2011, Page(s):1203 - 1210
Cited by:  Papers (40)
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A new class of positive linear systems consisting of n subsystems with different fractional orders is introduced. Solution to the set of matrix linear differential equations with different fractional orders is derived. Necessary and sufficient conditions for the positivity of the fractional systems are established. It is shown that the linear electrical circuits composed of resistors, super... View full abstract»

• ### Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Publication Year: 2011, Page(s):1211 - 1224
Cited by:  Papers (4)
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Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is p... View full abstract»

• ### A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

Publication Year: 2011, Page(s):1225 - 1238
Cited by:  Papers (21)
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In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loa... View full abstract»

• ### Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM

Publication Year: 2011, Page(s):1239 - 1251
Cited by:  Papers (12)
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Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-of-the-art SRAM designs employ replica timing control circuit to mitigate the effects of leakage and process variation, optimize the performance, and r... View full abstract»

• ### An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

Publication Year: 2011, Page(s):1252 - 1263
Cited by:  Papers (22)
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Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbance... View full abstract»

• ### A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines

Publication Year: 2011, Page(s):1264 - 1276
Cited by:  Papers (5)
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In this paper, a bus design scheme that achieves both impedance matching and uniform power distribution for a multidrop bus is presented. In contrast to conventional schemes, the proposed scheme lets the line impedance of each segment of the bus vary, and the impedance-matching resistance values are determined accordingly, thereby providing higher degrees of freedom for optimization. General formu... View full abstract»

• ### A Low-Cost VLSI Architecture for Robust Distributed Estimation in Wireless Sensor Networks

Publication Year: 2011, Page(s):1277 - 1286
Cited by:  Papers (7)
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A robust distributed estimation scheme for fusion center in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efficiently and improve the accuracy of the estimates significantly. It achieves very good performance at the expense of such extensive computations as logarithm and division in the ... View full abstract»

• ### Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images

Publication Year: 2011, Page(s):1287 - 1299
Cited by:  Papers (3)
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An infiltrative nature on ultrasound images is a significant feature of malignant breast lesion. Characterizing the infiltrative nature with highly efficacious and computationally inexpensive features is crucial for computer-aided diagnosis. The local variance can be characterized by a few high octave energies in the 1-D discrete periodized wavelet transform (DPWT). For the realization of high oct... View full abstract»

• ### Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC

Publication Year: 2011, Page(s):1300 - 1310
Cited by:  Papers (37)  |  Patents (1)
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This paper introduces an adaptive calibration structure for the blind calibration of frequency response mismatches in a two-channel time-interleaved analog-to-digital converter (TI-ADC). By representing frequency response mismatches as polynomials, we can exploit slight oversampling to estimate the coefficients of the polynomials by using the filtered-X least-mean square (FxLMS) algorithm. Utilizi... View full abstract»

• ### Efficient Design and Implementation of Variable Fractional Delay Filters Using Differentiators

Publication Year: 2011, Page(s):1311 - 1322
Cited by:  Papers (5)
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In this paper, the power series expansion of exponential function is used to transform the design problem of variable fractional delay (VFD) filter into the designs of digital differentiators with various orders such that conventional digital differentiators can be applied to implement VFD filter efficiently. The proposed method is flexible because the VFD filter can be designed by making the trad... View full abstract»

• ### Nonlinear Dynamics of Memristor Oscillators

Publication Year: 2011, Page(s):1323 - 1336
Cited by:  Papers (120)  |  Patents (1)
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A thorough investigation of the nonlinear dynamics of networks of memristor oscillators is a key step towards the design of systems based upon them, such as neuromorphic circuits and dense nonvolatile memories. A wide gamut of complex dynamic behaviors, including chaos, is observed even in a simple network of memristor oscillators, proposed here as a good candidate for the realization of oscillato... View full abstract»

• ### Controlling Chaos in a Memristor Based Circuit Using a Twin-T Notch Filter

Publication Year: 2011, Page(s):1337 - 1344
Cited by:  Papers (51)
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After the successful solid state implementation of memristors, a lot of attention has been drawn to the study of memristor based chaotic circuits. In this paper, a systematic study of chaotic behavior in such system is performed with the help of nonlinear tools such as bifurcation diagrams, power spectrum analysis, and Lyapunov exponents. In particular, a Twin-T notch filter feedback controller is... View full abstract»

• ### Lag Quasi-Synchronization of Coupled Delayed Systems With Parameter Mismatch

Publication Year: 2011, Page(s):1345 - 1357
Cited by:  Papers (41)
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This paper is concerned with lag synchronization of two coupled delayed systems with parameter mismatch. Due to parameter mismatch, complete lag synchronization can not be achieved. Therefore, a new lag quasi-synchronization scheme is proposed to ensure that coupled systems are in a state of lag synchronization with an error level. Several simple criteria are derived and the error level is estimat... View full abstract»

• ### Synchronization in Networks of Diffusively Time-Delay Coupled (Semi-)Passive Systems

Publication Year: 2011, Page(s):1358 - 1371
Cited by:  Papers (31)
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We consider networks with a general topology which consist of nonlinear systems that interact via diffusive coupling with constant time-delays. Using the notion of (semi-)passivity we prove under some mild assumptions that passive systems will synchronize and that the solutions of interconnected semi-passive systems will be bounded. Furthermore we prove that identical strictly semi-passive systems... View full abstract»

• ### In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

Publication Year: 2011, Page(s):1372 - 1381
Cited by:  Papers (5)
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For anti-fuse or flash-memory-based field-programmable gate arrays (FPGAs), single-event transient (SET)-induced faults are significantly more pronounced than single-event upsets (SEUs). While most existing work studies SEU, this paper proposes a retiming algorithm for mitigating variational SETs (i.e., SETs with different durations and strengths). Considering the reshaping effect of an SET pulse ... View full abstract»

• ### Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis

Publication Year: 2011, Page(s):1382 - 1395
Cited by:  Papers (60)
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This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) analog circuits. Nullators and norators along with the voltage mirror-current mirror (VM-CM) pair (collectively known as pathological elements) are used to model the behavior of active devices in voltage-, current-, and mixed-mode, also considering parasitic elements. Since a... View full abstract»

• ### Adaptive Synchronization of a Class of Uncertain Complex Networks Against Network Deterioration

Publication Year: 2011, Page(s):1396 - 1409
Cited by:  Papers (47)
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This paper is concerned with the robust synchronization problem for a class of uncertain dynamical complex networks against network deterioration. As deteriorated networks and uncertainties may lead to performance degradation or even instability of the whole network, an adaptive approach is proposed to adjust unknown coupling factors for the deteriorated network compensations, as well as to estima... View full abstract»

• ### A Counterexample to “ Positive Realness Preserving Model Reduction With ${cal H}_{infty}$ Norm Error Bounds”

Publication Year: 2011, Page(s):1410 - 1411
Cited by:  Papers (2)
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We provide a counterexample to the H∞ error bound for the difference of a positive real transfer function and its positive real balanced truncation stated in “Positive realness preserving model reduction with H∞ norm error bounds,” IEEE Trans. Circuits Syst, I, Fundam. Theory Appl., vol. 42, no. 1, pp. 23-29 (1995). The proof of the error bound is ... View full abstract»

• ### High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

Publication Year: 2011, Page(s):1412 - 1420
Cited by:  Papers (16)
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This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles.... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK