IEEE Transactions on Electron Devices

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Publication Year: 2011, Page(s):C1 - 1582
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2011, Page(s): C2
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• Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations

Publication Year: 2011, Page(s):1583 - 1593
Cited by:  Papers (22)
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This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large ve... View full abstract»

• Fabrication and Characterization of an Epitaxial Graphene Nanoribbon-Based Field-Effect Transistor

Publication Year: 2011, Page(s):1594 - 1596
Cited by:  Papers (13)
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The static and dynamic characteristics of top-gated graphene nanoribbon-based field-effect transistors were investigated. Multilayer graphene was synthesized by thermal decomposition of Si-face silicon carbide. The impact of the number of graphene layers on device performance was explored. It was found that, with the reduction of the layer number from ten to five, a significant improvement of dire... View full abstract»

• Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

Publication Year: 2011, Page(s):1597 - 1607
Cited by:  Papers (25)  |  Patents (1)
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In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-ox... View full abstract»

• Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs

Publication Year: 2011, Page(s):1608 - 1613
Cited by:  Papers (3)
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A gate-induced-drain-leakage-induced off-state breakdown is examined in our high-voltage depletion-mode n-channel metal-oxide-semiconductor field-effect transistors. By increasing the dosage in the n-region, a bell-shaped trend between the off-state breakdown voltage and the dosage in the n-region is observed. Such a bell-shaped trend is found to result from two competing factors: an electric fiel... View full abstract»

• Extended Quantum Correction Model Applied to Six-Band ${bf k}cdot {bf p}$ Valence Bands Near Silicon/Oxide Interfaces

Publication Year: 2011, Page(s):1614 - 1619
Cited by:  Papers (5)
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The modified local density approximation (MLDA) was developed to describe quantum corrections due to size quantization near a semiconductor-oxide interface for parabolic ellipsoidal bands. In this paper, we propose an extended MLDA model in order to consider arbitrary band structures. The results are compared with the original MLDA model and to self-consistent Poisson-Schrödinger solutions... View full abstract»

• A Novel Low-Voltage Low-Power Programming Method for NAND Flash Cell by Utilizing Self-Boosting Channel Potential for Carrier Heating

Publication Year: 2011, Page(s):1620 - 1627
Cited by:  Papers (4)
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A novel low-voltage low-power programming method for NAND Flash cell is presented. By utilizing the self-channel boosting technique, a sufficiently high local field is established in a NAND string that causes efficient hot-carrier injection. This method has been successfully demonstrated in the 75-nm-node floating-gate NAND cells, along with comprehensive studies on bias and timing effects. Requir... View full abstract»

• Scaling SOI MESFETs to 150-nm CMOS Technologies

Publication Year: 2011, Page(s):1628 - 1634
Cited by:  Papers (16)
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Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm ... View full abstract»

• Characteristics of $hbox{Si/SiO}_{2}$ Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method

Publication Year: 2011, Page(s):1635 - 1642
Cited by:  Papers (6)
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In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for complementary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measure... View full abstract»

• Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

Publication Year: 2011, Page(s):1643 - 1648
Cited by:  Papers (5)
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To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of acti... View full abstract»

• 30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

Publication Year: 2011, Page(s):1649 - 1654
Cited by:  Papers (29)
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This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the ION current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the ION current. The effects that ... View full abstract»

• Design and Optimization of Superjunction Collectors for Use in High-Speed SiGe HBTs

Publication Year: 2011, Page(s):1655 - 1662
Cited by:  Papers (11)
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After reviewing the various mechanisms causing breakdown in bipolar transistors, we present a novel collector design for silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The design improves the well-known speed/breakdown voltage tradeoff in SiGe HBTs for radio-frequency (RF) and millimeter-wave applications. Applying multiple alternating p- and n-type layers (a superjunction) deep... View full abstract»

• An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Publication Year: 2011, Page(s):1663 - 1671
Cited by:  Papers (9)  |  Patents (1)
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Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due ... View full abstract»

• Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

Publication Year: 2011, Page(s):1672 - 1680
Cited by:  Papers (7)
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The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experim... View full abstract»

• Effects of Barrier Thinning on Small-Signal and 30-GHz Power Characteristics of AlGaN/GaN Heterostructure Field-Effect Transistors

Publication Year: 2011, Page(s):1681 - 1686
Cited by:  Papers (9)
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Short-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with extremely thin AlGaN barrier layers were fabricated and characterized from the viewpoint of millimeter-wave applications. The devices showed good direct current and small-signal characteristics; however, the 30-GHz power characteristics were degraded due to frequency dispersion caused by the SiNx/AlGaN interface ... View full abstract»

• Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations

Publication Year: 2011, Page(s):1687 - 1695
Cited by:  Papers (5)
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This paper presents device models and optimization methodology for reducing short-channel effects in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), which are suitable for standard complementary metal-oxide-semiconductor (CMOS)-compatible analog operations. We analyze channel-length modulation to determine appropriate channel length having a single grain boundary in the ... View full abstract»

• Avalanche Gain and Energy Resolution of Semiconductor X-ray Detectors

Publication Year: 2011, Page(s):1696 - 1701
Cited by:  Papers (12)
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Realistic Monte Carlo simulations for the avalanche gain of absorbed X-ray photons were carried out in a study of the relationship between avalanche gain and energy resolution for semiconductor X-ray avalanche photodiodes (APDs). The work explored how the distribution of gains, which directly affects the energy resolution, depends on the number of injected electron-hole pairs (and, hence, the phot... View full abstract»

• Design and Characterization of Current-Assisted Photonic Demodulators in 0.18- $muhbox{m}$ CMOS Technology

Publication Year: 2011, Page(s):1702 - 1709
Cited by:  Papers (1)  |  Patents (3)
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We report on the design of a current-assisted photonic demodulator (CAPD) using standard 0.18-μm complementary metal-oxide-semiconductor technology and its electrooptical characterization. The device can perform both light detection and demodulation in the charge domain, owing to a drift field generated in the silicon substrate by a majority carrier flow. Minimum-sized 10 × 10 ;... View full abstract»

• A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Publication Year: 2011, Page(s):1710 - 1721
Cited by:  Papers (16)
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This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the dr... View full abstract»

• Design of an RF Transmit/Receive Switch Using LDMOSFETs With High Power Capability and Low Insertion Loss

Publication Year: 2011, Page(s):1722 - 1727
Cited by:  Papers (7)
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This paper presents, for the first time, the study of the application of a lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-LDMOSFET foundry technology. Measured results show that our switching ... View full abstract»

• TaN and $hbox{Al}_{2}hbox{O}_{3}$ Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

Publication Year: 2011, Page(s):1728 - 1734
Cited by:  Papers (1)
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The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI2O3/SiN/SiO2/Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI2O3 blocking-oxide layers and adversely affects the electrical performance and the m... View full abstract»

• Single-ZnO-Nanowire Memory

Publication Year: 2011, Page(s):1735 - 1740
Cited by:  Papers (45)
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Single-ZnO-nanowire (NW) memory based on resistive switching is demonstrated for the first time. The NW memory is stable, rewritable, and nonvolatile with on/off ratio up to 7.7 × 105. The O vacancies at the surfaces of ZnO NWs and around the interface of Ti/ZnO NWs observed using X-ray phototelectron spectroscopy, transmission electron microscopy (TEM), selected-area electron di... View full abstract»

• Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Publication Year: 2011, Page(s):1741 - 1747
Cited by:  Papers (18)
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An accurate method for extracting the depth and the energy level of an oxide trap from random telegraph noise (RTN) in the gate-induced drain leakage (GIDL) current of a metal-oxide-semiconductor field-effect transistor (MOSFET) is developed, which correctly accounts for variation in surface potential and Coulomb energy. The technique employs trap capture and emission times defined from the charac... View full abstract»

• Characteristic Degradation of Poly-Si Thin-Film Transistors With Large Grains From the Viewpoint of Grain Boundary Location

Publication Year: 2011, Page(s):1748 - 1751
Cited by:  Papers (4)
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The characteristic degradation of poly-Si thin-film transistors (TFTs) with large grains has been analyzed from the viewpoint of grain boundary location. Only when the grain boundary is located near the drain junction during bias stress, trap states are generated there due to the hot carriers, and the TFTs are severely degraded. Moreover, in the linear region, the transistor characteristics are de... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy