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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2011

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  • Table of contents

    Page(s): C1 - 1582
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations

    Page(s): 1583 - 1593
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (929 KB) |  | HTML iconHTML  

    This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs. View full abstract»

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  • Fabrication and Characterization of an Epitaxial Graphene Nanoribbon-Based Field-Effect Transistor

    Page(s): 1594 - 1596
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    The static and dynamic characteristics of top-gated graphene nanoribbon-based field-effect transistors were investigated. Multilayer graphene was synthesized by thermal decomposition of Si-face silicon carbide. The impact of the number of graphene layers on device performance was explored. It was found that, with the reduction of the layer number from ten to five, a significant improvement of direct-current characteristics and high-frequency performance can be observed. A high intrinsic current-gain cutoff frequency of 60 GHz and a maximum oscillation frequency of 28 GHz are reported. View full abstract»

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  • Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

    Page(s): 1597 - 1607
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    In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development. View full abstract»

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  • Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs

    Page(s): 1608 - 1613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB) |  | HTML iconHTML  

    A gate-induced-drain-leakage-induced off-state breakdown is examined in our high-voltage depletion-mode n-channel metal-oxide-semiconductor field-effect transistors. By increasing the dosage in the n-region, a bell-shaped trend between the off-state breakdown voltage and the dosage in the n-region is observed. Such a bell-shaped trend is found to result from two competing factors: an electric field in the gate edge and an electric field associated with the drain-bulk junction. The latter electric field is responsible for the falling part in the bell-shaped trend. Our model can explain the data of the slightly bell-shaped trend between off-state and implant energy in the n-region. Additionally, the effect of Si recess variation on off-state variation can be understood from our model. According to our model, approaches to improve off-state and the effect of Si recess variation on variation are proposed. View full abstract»

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  • Extended Quantum Correction Model Applied to Six-Band {\bf k}\cdot {\bf p} Valence Bands Near Silicon/Oxide Interfaces

    Page(s): 1614 - 1619
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    The modified local density approximation (MLDA) was developed to describe quantum corrections due to size quantization near a semiconductor-oxide interface for parabolic ellipsoidal bands. In this paper, we propose an extended MLDA model in order to consider arbitrary band structures. The results are compared with the original MLDA model and to self-consistent Poisson-Schrödinger solutions using both constant effective mass and confined six-band Hamiltonians. The extended MLDA model is verified for three major surface orientations and high stress conditions. View full abstract»

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  • A Novel Low-Voltage Low-Power Programming Method for NAND Flash Cell by Utilizing Self-Boosting Channel Potential for Carrier Heating

    Page(s): 1620 - 1627
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    A novel low-voltage low-power programming method for NAND Flash cell is presented. By utilizing the self-channel boosting technique, a sufficiently high local field is established in a NAND string that causes efficient hot-carrier injection. This method has been successfully demonstrated in the 75-nm-node floating-gate NAND cells, along with comprehensive studies on bias and timing effects. Requirements for high-voltage supporting devices, circuitry, and process in conventional Fowler-Nordheim programmed NAND cells are greatly mitigated. It would be very attractive for scaled NAND Flash technology in the future. View full abstract»

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  • Scaling SOI MESFETs to 150-nm CMOS Technologies

    Page(s): 1628 - 1634
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    Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm. View full abstract»

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  • Characteristics of \hbox {Si/SiO}_{2} Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method

    Page(s): 1635 - 1642
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    In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for complementary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measurements simultaneously. For n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), devices with the increased defect-removal annealing time bring out a significant decrease in the CP current and the 1/f noise. The results indicate that ATR-induced defects are further repaired and consequently achieve a well Si/SiO2 interface. In addition, the driving current improvement is observed in devices with a small dimension utilizing the modified ATR process. For p-type MOSFETs (pMOSFETs), the direct-current characteristic, CP, and 1/f noise results are comparable between both HOT wafers. It means that the modified process would not affect bonded (110) regions and degrade the device performance. Hence, this modified process could be adopted to improve the fabrication of the CMOS on the HOT wafer using the ATR method. Moreover, the physical origins of the 1/f noise is attributed to a fluctuation in the mobility of free carriers for pMOSFETs and a unified model, incorporating both the carrier- number and correlated mobility fluctuations, for nMOSFETs. View full abstract»

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  • Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

    Page(s): 1643 - 1648
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (593 KB) |  | HTML iconHTML  

    To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in tret on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, we successfully distinguished the two types of trap models. View full abstract»

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  • 30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

    Page(s): 1649 - 1654
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB) |  | HTML iconHTML  

    This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the ION current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the ION current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate. View full abstract»

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  • Design and Optimization of Superjunction Collectors for Use in High-Speed SiGe HBTs

    Page(s): 1655 - 1662
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    After reviewing the various mechanisms causing breakdown in bipolar transistors, we present a novel collector design for silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The design improves the well-known speed/breakdown voltage tradeoff in SiGe HBTs for radio-frequency (RF) and millimeter-wave applications. Applying multiple alternating p- and n-type layers (a superjunction) deep in the collector-base (CB) space-charge region (SCR) alters the electric field and electron temperature in the CB junction. Consequently, impact ionization is suppressed, whereas the width of the CB SCR is not increased, and therefore, the breakdown voltages BVCEO and BVCEO are increased, with no degradation in the device speed or RF performance. For a fixed alternating-current performance, BVCEO is improved by 0.33 V, producing a SiGe HBT with fT = 101 GHz, fmax = 351 GHz, and BVCEO = 3.0 V, as predicted by calibrated DESSIS technology computer-aided design simulations. Concerns with regard to the influence of thermal cycles associated with fabrication are considered, and a more practical doping profile is proposed to simplify the use of superjunctions. The proposed structure is also contrasted with other approaches from the literature. View full abstract»

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  • An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

    Page(s): 1663 - 1671
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB) |  | HTML iconHTML  

    Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. View full abstract»

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  • Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

    Page(s): 1672 - 1680
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experimental one of polycrystalline silicon lines, which were formed using plasma etching. The authors investigate the effect of LER/LWR on the current factor of metal-oxide-semiconductor field-effect-transistors, comparing this to conventional models. The Gaussian ACF, which is widely used in device simulations, calculates the variation in the current factor with considerable accuracy as long as accurate LER/LWR statistics are used. However, it alone cannot provide the statistics. The exponential ACF underestimates the variation by a nonnegligible amount. From these results, the authors propose to use the aforementioned smoothed exponential ACF in the device simulations. They also alert to the possibility that a little-known long-range correlation exists universally in the LER/LWR even of the present-day devices and is causing an unexpectedly large mismatching between wide-channel devices. View full abstract»

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  • Effects of Barrier Thinning on Small-Signal and 30-GHz Power Characteristics of AlGaN/GaN Heterostructure Field-Effect Transistors

    Page(s): 1681 - 1686
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    Short-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with extremely thin AlGaN barrier layers were fabricated and characterized from the viewpoint of millimeter-wave applications. The devices showed good direct current and small-signal characteristics; however, the 30-GHz power characteristics were degraded due to frequency dispersion caused by the SiNx/AlGaN interface states. The dispersive behavior of the thin barrier devices measured in pulse I-V curves was different from the commonly observed one for the devices with normal AlGaN barrier thicknesses of 20-30 nm. The first characteristic point was that it happened only for structures with extremely thin barrier layers. As another unique point, the drain current collapse in the pulsed modes was observed only at a positive gate bias. We consider that the unique dispersion of the thin barrier HFETs was caused by the different charging paths related to hot electrons accelerated in a high electric field region of a 2-D electron gas (2DEG) channel. It seems reasonable to suppose that, for the extremely thin barrier structures, the AlGaN surface states can be charged not only by injected electrons from the gate metal through the SiNx/AlGaN interface but also by the hot electrons overcoming the barrier from the 2DEG formed at the AlGaN/GaN interface. View full abstract»

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  • Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations

    Page(s): 1687 - 1695
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    This paper presents device models and optimization methodology for reducing short-channel effects in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), which are suitable for standard complementary metal-oxide-semiconductor (CMOS)-compatible analog operations. We analyze channel-length modulation to determine appropriate channel length having a single grain boundary in the channel fabricated using excimer laser-annealed crystallization under low-temperature constraint. Furthermore, buried-oxide-induced barrier lowering (BIBL) is investigated in poly-Si TFTs. BIBL makes the effective channel length shorter, resulting in difficulty to use LTPS TFTs for analog applications due to small output resistance rout. We show that, with scaling of the buried-oxide (BOX) thickness Tbox and an appropriate channel length, rout and the normalized transconductance gm/Id (with Tbox = 10 nm) can be improved by 103% and 8%, respectively, compared with thicker BOX (Tbox = 50 nm). In addition, due to the decrease in leakage currents, the Ion/Ioff ratio of the thin-BOX device can be three times larger than that of the thicker BOX device. Based on the process-constrained optimized device, we designed a 417-μW 65-dB folded-cascode operational amplifier with 2-V supply for CMOS-compatible operations. View full abstract»

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  • Avalanche Gain and Energy Resolution of Semiconductor X-ray Detectors

    Page(s): 1696 - 1701
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    Realistic Monte Carlo simulations for the avalanche gain of absorbed X-ray photons were carried out in a study of the relationship between avalanche gain and energy resolution for semiconductor X-ray avalanche photodiodes (APDs). The work explored how the distribution of gains, which directly affects the energy resolution, depends on the number of injected electron-hole pairs (and, hence, the photon energy), the relationship between ionization coefficients, and the mean gain itself. We showed that the conventional notion of APD gains significantly degrading energy resolution is incomplete. If the X-ray photons are absorbed outside the avalanche region, then high avalanche gains with little energy resolution penalty can be achieved using dissimilar ionization coefficients. However, absorption of X-ray photons within the avalanche region will always result in broad gain distribution (degrading energy resolution), unless electrons and holes have similar ionization coefficients. View full abstract»

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  • Design and Characterization of Current-Assisted Photonic Demodulators in 0.18- \mu\hbox {m} CMOS Technology

    Page(s): 1702 - 1709
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    We report on the design of a current-assisted photonic demodulator (CAPD) using standard 0.18-μm complementary metal-oxide-semiconductor technology and its electrooptical characterization. The device can perform both light detection and demodulation in the charge domain, owing to a drift field generated in the silicon substrate by a majority carrier flow. Minimum-sized 10 × 10 μm2 CAPDs exhibit a direct-current charge-transfer efficiency larger than 80% (corresponding to demodulation contrast larger than 40% under sine-wave modulation) at the modest power consumption of 10 μW and a 3-dB bandwidth of >; 45 MHz. An excellent linearity value with an error lower than 0.11% is obtained in phase measurements. CAPDs with optimized modulation electrode geometries are finally designed, aiming at an improved contrast-versus-power tradeoff. View full abstract»

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  • A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

    Page(s): 1710 - 1721
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    This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standard charge-sheet MOS model for the low-voltage part adds up to a complete HV-MOSFET model, which is verified against technology computer-aided design simulations and measurements of HV-MOS transistors. The comparisons demonstrate its accurate physics foundations and underline that this novel approach to the modeling of the drift region of the HV-MOSFET is promising. View full abstract»

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  • Design of an RF Transmit/Receive Switch Using LDMOSFETs With High Power Capability and Low Insertion Loss

    Page(s): 1722 - 1727
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    This paper presents, for the first time, the study of the application of a lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. View full abstract»

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  • TaN and \hbox {Al}_{2}\hbox {O}_{3} Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

    Page(s): 1728 - 1734
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    The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI2O3/SiN/SiO2/Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI2O3 blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive AI2O3 high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-μm-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged AI2O3 region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length. View full abstract»

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  • Single-ZnO-Nanowire Memory

    Page(s): 1735 - 1740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    Single-ZnO-nanowire (NW) memory based on resistive switching is demonstrated for the first time. The NW memory is stable, rewritable, and nonvolatile with on/off ratio up to 7.7 × 105. The O vacancies at the surfaces of ZnO NWs and around the interface of Ti/ZnO NWs observed using X-ray phototelectron spectroscopy, transmission electron microscopy (TEM), selected-area electron diffraction, and high-resolution TEM might play a role in the resistive switching behavior. The endurance of resistive switching can be enhanced by further increasing the sweeping voltage. This paper brings an exciting possibility of building next-generation memory devices based on NWs. View full abstract»

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  • Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

    Page(s): 1741 - 1747
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    An accurate method for extracting the depth and the energy level of an oxide trap from random telegraph noise (RTN) in the gate-induced drain leakage (GIDL) current of a metal-oxide-semiconductor field-effect transistor (MOSFET) is developed, which correctly accounts for variation in surface potential and Coulomb energy. The technique employs trap capture and emission times defined from the characteristics of GIDL. Ignoring this variation in surface potential leads to an error of up to 116% in trap depth for 80-nm technology generation MOSFETs. RTN amplitude as a function of MOSFET drain-gate voltage is also investigated. View full abstract»

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  • Characteristic Degradation of Poly-Si Thin-Film Transistors With Large Grains From the Viewpoint of Grain Boundary Location

    Page(s): 1748 - 1751
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (514 KB) |  | HTML iconHTML  

    The characteristic degradation of poly-Si thin-film transistors (TFTs) with large grains has been analyzed from the viewpoint of grain boundary location. Only when the grain boundary is located near the drain junction during bias stress, trap states are generated there due to the hot carriers, and the TFTs are severely degraded. Moreover, in the linear region, the transistor characteristics are degraded wherever the grain boundary is located. On the other hand, in the saturation region, the transistor characteristics are degraded when the grain boundary is located near the source junction, whereas the transistor characteristics are not degraded very much when the grain boundary is located near the drain junction. This paper is the first report to give an experimental example of the aforementioned phenomenon, which was conjectured using 2-D device simulation. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology