By Topic

Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 5 • Date May 2011

Filter Results

Displaying Results 1 - 25 of 26
  • [Front cover]

    Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (178 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): i - ii
    Save to Project icon | Request Permissions | PDF file iconPDF (152 KB)  
    Freely Available from IEEE
  • Effects of Acid Electrolytes and Electropolishing Conditions on Laser-Stencil Printing Performance

    Page(s): 641 - 646
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (701 KB) |  | HTML iconHTML  

    The electropolishing process has shown promising results for improving the surface finish of small apertures in laser-stencils. We report on the results of the investigations of the parameters that control the electropolishing process using highly concentrated phosphoric acid. The effect of the phosphoric acid solution on the finish of the polished small apertures and the effect of the electropolishing time were investigated. An optimized process was established through inspection of the polished stencil apertures of the laser-stencil. The results demonstrated that the acid solution for the electrolyte as well as the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil-printing performance. In particular, a 95 wt.% phosphoric acid-based electrolyte showed encouraging results in terms of surface smoothness, improved solder-paste printing, and surface-mount-technology yields. The most effective electropolishing times were 5, 10, and 20 s for stencils thicknesses of 0.05, 0.08, and 0.10 mm, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interface Formation Between Metal and Polyimide in High Wiring Density Build-up Substrate

    Page(s): 647 - 652
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    A key to a high-wiring-density build-up substrate is fine circuitry formation technology to satisfy the ever-increasing demands for miniaturization of electronics products. The surface roughness of a dielectric layer needs to be in the submicrometer scale for fine circuitry such as a line less than 10 μm wide. However, the Cu to dielectric adhesion strength of such a line would not be sufficient to prevent peeling off during manufacture and after heat treatment. Consequently, it is essential to have good adhesion between Cu and dielectric layer with chemical bonds between the metal and the dielectric layer. A polyimide film was introduced as a dielectric layer in a build-up substrate. Argon plasma-modified polyimide surfaces were sputtered with NiCr and then subjected to Cu electroplating. While unmodified polyimide had a weak adhesion strength of 0.12 kN m-1, Ar plasma-modified polyimide showed good adhesion strength of more than 0.5 kN m-1 even after 10 days of heat treatment at 172°C. X-ray photoelectron spectroscopy studies revealed that the adhesion strength was attributable to chemical bonds between Cr and the polyimide. Ar plasma-treated polyimide produced a large quantity of oxygen functional groups containing C=O bonds on the surface of polyimide, and subsequent NiCr sputtering produced C-O-Cr or C=O⋯Cr bonds to the polyimide. In addition, NiCr sputtering also attacked some of N-C=O and N-C bonds, and modified them to produce C-N-Cr or C-N⋯Cr bonds to the polyimide. These two types of mechanism produced sufficiently high Cu to polyimide adhesion to achieve fine line circuitry. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New Silver Paste for Die-Attaching Ceramic Light-Emitting Diode Packages

    Page(s): 653 - 659
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB) |  | HTML iconHTML  

    Micrometer-sized Ag particles adsorb substantial oxygen above 200°C and a dispersion of these particles in alcohol can be successfully used as a die-attach material by sintering to form a soft porous bonding layer. The characteristics of a light-emitting diode (LED) using this Ag paste as a die-attach material were evaluated. The LED was assembled on an alumina ceramic package, which did not degrade upon sintering, with a sapphire-based InGaN LED die. The bonding strength was twice as high to the ceramic package as to a copper alloy lead frame. Thus, the Ag paste is suitable for use with LED ceramic packages as a bonding material. In addition, a significant reduction of the thermal resistance and improvement of the reliability are achieved by using the Ag sintered layer for die-attaching the ceramic LED package. To improve the bond reliability between sapphire and alumina, both of which are low-thermal-expansion materials, the thermal expansion of the Ag sintered layer was reduced by the addition of Kovar particles. The addition of Kovar particles, with or without Ag plating, to Ag particles exhibited a desirable effect. The present mounting method for LEDs was proved to be useful for die-bonding electronic components, providing an alternative technique to high-temperature high-lead soldering. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of Large Die Fine-Pitch Cu/Low- k FCBGA Package With Through Silicon via (TSV) Interposer

    Page(s): 660 - 672
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1150 KB) |  | HTML iconHTML  

    The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

    Page(s): 673 - 680
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1162 KB) |  | HTML iconHTML  

    This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Coplanar-to-Rectangular Waveguide Transitions Using Slot Antennas

    Page(s): 681 - 688
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    A coplanar-to-rectangular waveguide transition using a dipole slot antenna is proposed in this paper. The advantage of this transition is that no intermediate transition and vias are needed in this direct transition. Parameter studies of this transition demonstrate that a transition having a fractional bandwidth of 22.85%, for which the return loss is larger than 15 dB, is achieved in the X-band (8.2-12.4 GHz). Furthermore, in order to enhance the bandwidth, the dipole slot antenna is replaced by a bowtie slot antenna. This design demonstrates a wider fractional bandwidth of 26.67%. Back-to-back transitions for both designs were fabricated and measured in order to verify these designs, and the measurement results agree well with the simulation results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Feature-Extraction-Based Inspection Algorithm for IC Solder Joints

    Page(s): 689 - 694
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB) |  | HTML iconHTML  

    In order to inspect solder joint defects of integrated circuit (IC) components on printed circuit boards (PCBs), an automatic optical inspection (AOI) algorithm is developed. Firstly, considering the shape of a solder joint and its optical reflection property, the IC solder joint is divided into several subregions, which are called shape features. Secondly, the digital features that are used to evaluate the solder quality of the subregions are expressed by the color, area, mass center, and continuous pixels. Thirdly, the logical features are developed according to the color distributions of the solder joint image and the relationships between different subregions and the types of solder joints. Finally, to evaluate the performance of the proposed algorithm, 137 PCBs with defects were inspected by an AOI system that integrates with the proposed algorithm. Inspection results show that solder joint defects of IC such as surplus solder, lacking solder, no solder, lead lift, lead bend, shift, and bridged and pseudo joints can be identified effectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical Modeling of Cyclic Thermal Stress and Strain in Plated-Through-Vias With Defects

    Page(s): 695 - 704
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    A previously published analytical model for thermal stress and strain in idealized plated-through-vias (PTVs) has been adapted to conduct elastic-plastic analyses of vias with geometric defects using elastic stress concentration factors calculated earlier. The von Mises stress amplitude, at the mid-plane of the perfect via and at the defect (Δσ0 and Δσ, respectively), and the cumulative plastic von Mises strain, also at the mid-plane of a perfect via and at a defect (ε0pl and εpl, respectively), compared well with results of finite element analyses (FEAs). Four types of PTV defects were evaluated: barrel thickness reduction, occasional waviness, continuous waviness, and wicking. This model provides a relatively simple alternative to FEA to calculate stresses and strains in vias with defects as well as in perfect vias subjected to multiple thermal cycles. This model provides a tool to investigate quickly the influence of possible PTV design dimensions and defects under thermal cycling conditions (i.e., which are particularly damaging in a given situation). It is much easier than FEA for parametric studies like this. It also provides a means for calculating damage metrics, such as the cumulative von Mises strain, which can then be empirically correlated with the cycles to failure data from thermal cycling tests of PTVs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-Cooling on Germanium Chip

    Page(s): 705 - 713
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1082 KB) |  | HTML iconHTML  

    As the scaling of silicon complementary metal-oxide-semiconductor devices becomes more and more challenging, both innovative device structures and new materials with high carrier mobility are needed to continue improving device performances. A metal-oxide-semiconductor field-effect transistor with germanium channel currently receives a resurgence of interest as a possible candidate for next-generation high mobility devices because germanium offers much higher mobility for both electrons and holes in comparison with silicon. While germanium solid-state device provides outstanding electrical benefits, it also offers significant challenges in thermal management and raises a major concern over the effect of on-chip hot spot on the reliability and performance of germanium chips. Current thermal management technologies, with a major focus on chip-level global cooling, offer very few choices for on-chip micro-scale hot spot cooling. The inherent thermoelectric properties of single crystal germanium support development of a novel thermal management strategy for micro-scale hot spot cooling which relies on thermoelectric self-cooling by electric current flowing into the back of the germanium chip. In this paper, the concept of germanium self-cooling for on-chip micro-scale hot spot is proposed and investigated. 3-D thermal-electric coupling simulations are used to evaluate the hot spot cooling performance on a germanium chip with a wide range of system parameters, including applied current, doping concentration, hot spot heat flux, micro-cooler size, and germanium chip thickness. The results suggest that localized thermoelectric self-cooling on the germanium chip can effectively reduce the temperature rise resulting from micro-scale high heat flux hot spots and shows a great promise as a novel on-chip cooling solution. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Isothermal Aging Effects on the Mechanical Shock Performance of Lead-Free Solder Joints

    Page(s): 714 - 721
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB) |  | HTML iconHTML  

    Isothermal aging effects on lead-free solders have been extensively investigated in recent studies. Researches show that aging effects significantly degrade the mechanical properties of lead-free solders. However, limited work has been done on the effects of aging on the board-level dynamic performance of lead-free solder joints, especially for large flip-chip ball grid array (FCBGA) packages. Due to the sensitivity of aging effects on lead-free solders, it is crucial to investigate the aging effects on the board-level dynamic performance of lead-free solders. In this paper, dynamic performance of lead-free solder joints has been characterized and isothermal aging effects have been investigated. It was found that the dynamic shock performance of lead-free FCBGA packages significantly degrades up to 20-35% after aging at elevated temperatures. It was also observed that aging at 100°C shows more severe degradation than aging at 75°C and 150°C. This is an important finding because many electronic products operate in the 100°C range for long periods. The unique finding of aging effects is related to the growth of Cu3Sn and Cu6Sn5 intermetallics after aging. Even though failure analysis shows mixed failure of pad cratering and intermetallic compound (IMC) failures, the IMC growth is the most sensitive factor contributing to the failure observed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Differential Via Modeling Methodology

    Page(s): 722 - 730
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (953 KB) |  | HTML iconHTML  

    This paper describes a novel method of modeling the differential via on multilayered printed circuit boards (PCBs) used in high-speed digital designs based on the analytical equations for characteristic impedance and effective dielectric constant. In the absence of measured or electromagnetic simulated data traditionally needed to extract these parameters, this method can quickly and efficiently predict the behavior of the differential via holes on PCBs using a circuit simulator. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Equivalent-Circuit Modeling for Multilayer Capacitors Based on Coupled Transmission-Line Theory

    Page(s): 731 - 741
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1141 KB) |  | HTML iconHTML  

    This paper provides a novel modeling methodology for multilayer capacitors (MLCs) based on the coupled transmission-line theory. From an analytical solution of a single-layer capacitor, first- and second-order equivalent-circuit models for an N-layer capacitor are introduced using an infinite series approximation. The models demonstrated accurate prediction of the behavior of MLCs up to the first and second self-resonant frequencies. In addition, distributed physical parameters for the models were extracted directly from S-parameter measurements without an optimization process. High-frequency MLCs were measured up to 20 GHz using a vector network analyzer and compared with models from 1 to 47 pF. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compensation Design for DC Blocking Multilayer Ceramic Capacitor in High-Speed Applications

    Page(s): 742 - 751
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1007 KB) |  | HTML iconHTML  

    The shunt parasitic capacitance of a multilayer ceramic capacitor (MLCC) mounting structure seriously degrades the performance of the MLCC in high-speed applications. In this paper, we propose a new compensation design method with which the reference planes underneath the surface mount technology pads and MLCC are cleared to eliminate the excessive capacitance effect. An analytical model is derived to compute the optimal clear parameters using conformal mapping, and the result of the analytical model closely matches with that of Ansoft 2-D Extractor. It is convenient for the printed circuit board (PCB) designer to utilize this model to obtain the optimal compensation parameters without building the 2-D or 3-D models of the MLCC mounting structure. Simulation and measurement results show that the compensation design is effective in improving the signal integrity of dc blocking MLCCs mounted on high-speed PCBs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel Time-Domain Finite-Element Simulator of Linear Speedup and Electromagnetic Accuracy for the Simulation of Die–Package Interaction

    Page(s): 752 - 760
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (685 KB) |  | HTML iconHTML  

    In this paper, we develop an almost embarrassingly parallel solution to an electromagnetic solver of linear complexity for overcoming the grand challenge of performing electromagnetically accurate co-simulation of die-package interaction. In this solution, through suitable basis functions and linear algebraic techniques, we directly and rigorously decompose the system matrix in a 3-D space to multiple matrices of 1-D sizes with negligible computational overhead. Each 1-D matrix is made tridiagonal and, hence, can be solved readily in linear complexity. We then achieve an almost embarrassingly parallel implementation of the fast electromagnetic solver with a low communication-to-computation ratio. Numerical experiments on a large-scale combined die-package system, involving more than 3.5 billion unknowns, have demonstrated superior performance of the proposed parallel transient simulator for simulating large-scale integrated circuits and package problems. In addition, the proposed solver is applicable to any arbitrarily shaped multilayer structure embedded in inhomogeneous materials. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Modeling of Power/Ground Planes Using Delay-Extraction-Based Transmission Lines

    Page(s): 761 - 771
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (705 KB) |  | HTML iconHTML  

    This paper presents an efficient approach for modeling irregular shaped power distribution networks (PDN) in high-speed packages. The proposed methodology is based on discretization of the plane into an orthogonal grid of transmission line segments. Using a delay-extraction-based model for each line segment, a compact circuit model is achieved where the size of the circuit matrices depend only on the nodes of the orthogonally discretized structure and all other internal nodes due to the macromodel are eliminated. This approach of eliminating the internal variable due to the transmission line macromodel is further extended to model skin effect losses without augmenting the circuit matrices. The proposed work has been successfully implemented for a variety of PDN structures and geometries and has been shown to yield significant savings in memory and run time costs compared to the existing simulation program with integrated circuits emphasis macromodels. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hybrid Statistical Link Simulation Technique

    Page(s): 772 - 783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1533 KB) |  | HTML iconHTML  

    Accurate analysis of link performance including deterministic and random effects as well as advanced signal conditioning schemes is crucial in modern high-speed I/O design. In recent years, statistical link performance tools such as LinkLab and StatEye are introduced to efficiently analyze the overall link performance with both deterministic and random noise. The statistical-domain analysis has limitations in terms of its capability of accurately simulating system nonlinearity, jitter, as well as coding. In this paper, we present a new hybrid approach that combines statistical and time-domain techniques to efficiently overcome these limitations. The proposed method has several key contributions: 1) capture system nonlinearity; 2) separately simulate short-term deterministic jitter in the time domain and long-term deterministic and random jitter in the statistical domain; 3) co-simulate clock and data channels to capture jitter tracking; and 4) co-simulate signal and power integrity to include simultaneous switching output noise. We demonstrate this hybrid approach by studying the jitter tracking capability of a clock forwarding scheme and the effectiveness of coding in terms of system bit error rate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of Failure Rate by Column Distribution in Magnetically Aligned Anisotropic Conductive Adhesive

    Page(s): 784 - 791
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (826 KB) |  | HTML iconHTML  

    Characteristics of z-axis interconnects using magnetically aligned anisotropic conductive adhesives (ACAs) are analyzed for their applicability for small pad sizes. In order to evaluate the performance of ACAs, a statistical estimation of the failure rate of interconnects was carried out using top-view images of assembled samples. Through a column mapping process, the failure rate is calculated as a function of pad size. The calculated and measured results indicate that the location of the formed columns is the predominant effect determining interconnect failure. The developed failure estimation approach is effective in demonstrating the effects of scaling to smaller particles in ACAs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wafer-Level Packages Using Anisotropic Conductive Adhesives (ACAs) Solution for Flip-Chip Interconnections

    Page(s): 792 - 797
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    In this paper, wafer-level packages (WLPs) using an anisotropic conductive adhesives (ACAs) solution have been newly developed for flip-chip interconnections. WLPs using ACAs (ACA-WLPs) reduce processing steps compared to WLPs using anisotropic conductive films (ACFs), because ACA solution is directly coated on a wafer without an ACF formation process on the releasing film and an ACF lamination process on the wafer. The effects of ACA coating process parameters, such as blade gap and temperature, were first investigated for a uniform thickness coating without voids on an Au-bumped wafer. After solvent drying and subsequent singulation of a B-stage ACA-coated wafer, a singulated chip was flip-chip assembled on an organic substrate using a thermo-compression bonding method. The reliabilities of flip-chip assemblies using ACA-WLPs were evaluated in terms of a high temperature/humidity test, thermal cycling test, and pressure cooker test (PCT) and compared with corresponding results of conventional ACF flip-chip assemblies. In the high temperature/humidity reliability test and thermal cycling test, there was no difference in the flip-chip reliabilities between the two types of flip-chip assemblies. Furthermore, the flip-chip assemblies using ACA-WLPs showed better PCT reliability than the conventional ACF flip-chip assemblies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solder Joint Reliability of SnAgCu Solder Refinished Components Under Temperature Cycling Test

    Page(s): 798 - 808
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1202 KB) |  | HTML iconHTML  

    SnAgCu (SAC) solder is being offered as a lead-free termination finish. SAC finish is obtained by dipping the terminals of components into molten SAC solder. However, the reliability of solder joints formed with SAC solder refinished components needs to be determined in order to evaluate the effects of the SAC solder refinishing process. In this paper, the strength of solder joints with SAC solder refinished thin small outline packages (TSOPs) was evaluated by the shear test. The reliability of solder joints formed with SAC solder refinished components, including TSOPs and resistors, was evaluated by a temperature cycling test. Original Sn finished components were used as a baseline for comparison. It was found that SAC solder refinishing increased solder joint strength. SAC solder refinishing decreased the fatigue life of solder joints of TSOPs and increased the fatigue life of resistors under temperature cycling conditions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Blank page

    Page(s): 809 - 810
    Save to Project icon | Request Permissions | PDF file iconPDF (6 KB)  
    Freely Available from IEEE
  • 2011 IEEE membership form

    Page(s): 811 - 812
    Save to Project icon | Request Permissions | PDF file iconPDF (1361 KB)  
    Freely Available from IEEE
  • IEEE Components, Packaging, and Manufacturing Technology Society information for authors

    Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (21 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University