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IEEE Design & Test of Computers

Issue 3 • May-June 2011

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Displaying Results 1 - 25 of 25
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Front cover]

    Publication Year: 2011, Page(s): c2
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  • Call for Papers

    Publication Year: 2011, Page(s): 1
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  • Contents

    Publication Year: 2011, Page(s):2 - 3
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  • Toward Bug-free Multicore SoC Architectures: System Validation with Transaction-Level Models

    Publication Year: 2011, Page(s): 4
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  • [Masthead]

    Publication Year: 2011, Page(s): 5
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  • Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models

    Publication Year: 2011, Page(s):6 - 9
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  • Automatic TLM Generation for Early Validation of Multicore Systems

    Publication Year: 2011, Page(s):10 - 19
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    This article suggests a methodology to validate software applications for a multicore platform by automatically generating transaction-level models from task-level specification of the applications. Software vendors developing applications for multicore platforms can leverage this methodology for early validation. View full abstract»

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  • Transaction-Level Validation of Multicore Architectures 
  • Multicore Simulation of Transaction-Level Models Using the SoC Environment

    Publication Year: 2011, Page(s):20 - 31
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1148 KB) | HTML iconHTML

    Editor's note: To address the limitations of discrete-event simulation engines, this article presents an extension of the SoC simulation kernel to support parallel simulation on multicore hosts. The proposed optimized simulator enables fast validation of large multicore SoC designs by issuing multiple simulation threads simultaneously while ensuring safe synchronization. View full abstract»

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  • On MPSoC Software Execution at the Transaction Level

    Publication Year: 2011, Page(s):32 - 43
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (938 KB) | HTML iconHTML

    This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation. View full abstract»

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  • Interactive Debug of SoCs with Multiple Clocks

    Publication Year: 2011, Page(s):44 - 51
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB) | HTML iconHTML

    Systems with elaborate multiple clock distributions are a necessity, and the authors address the postfabrication debug of such multiclock systems. Solutions, based on the authors' communication-centric debug approach, are presented that achieve a consistent snapshot of the system state and force the erroneous state in the face of nondeterminism. View full abstract»

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  • Challenges of Rapidly Emerging Consumer Space Multiprocessors

    Publication Year: 2011, Page(s):52 - 53
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (81 KB) | HTML iconHTML

    In the computer systems industry, roughly between the years 1950 and 1980, the advances in technology were largely aimed at high-end or enterprise-class hardware.For the next 30 years, the personal computing industry was the arena in which technological advances were applied. For the past couple years, technological trailblazing has been led by consumer electronics, such as smartphones, tablets, a... View full abstract»

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  • Selective Hardening: Toward Cost-Effective Error Tolerance

    Publication Year: 2011, Page(s):54 - 63
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2227 KB) | HTML iconHTML

    As ICs shrink into the nanometer range, they are increasingly subject to errors induced by physical faults. Traditional hardening for error mitigation consumes too much area and energy to be cost-effective in commercial applications. Selective hardening, applied only to a design's most error-sensitive parts, offers an attractive alternative. This article reviews recently proposed techniques to sel... View full abstract»

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  • Postproduction Performance Calibration 
  • Improving Analog and RF Device Yield through Performance Calibration

    Publication Year: 2011, Page(s):64 - 75
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1251 KB) | HTML iconHTML

    As the semiconductor industry continues scaling devices toward smaller process nodes, maintaining acceptable yields despite process variations has become increasingly challenging. Analog and RF circuits are particularly sensitive to process variations. This article discusses the challenges of cost-effective postfabrication performance calibration in such analog and RF devices and introduces a sing... View full abstract»

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  • Three Misconceptions Regarding Standards

    Publication Year: 2011, Page(s):76 - 79
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  • All About Liquid Scan Chains— and More [review of "Digital Microfluidic Biochips: Design Automation and Optimization" (Chakrabarty, K. and Xu, T.; 2010)]

    Publication Year: 2011, Page(s):80 - 81
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  • Conference Reports

    Publication Year: 2011, Page(s):82 - 83
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  • Panel Summaries

    Publication Year: 2011, Page(s):84 - 85
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  • The Future of Signoff

    Publication Year: 2011, Page(s):86 - 89
    Cited by:  Papers (1)
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  • CEDA Currents

    Publication Year: 2011, Page(s):90 - 91
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  • Test Technology TC Newsletter

    Publication Year: 2011, Page(s):92 - 93
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  • Design Automation Technical Committee Newsletter

    Publication Year: 2011, Page(s):94 - 95
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  • A Brief History of Multiprocessors and EDA

    Publication Year: 2011, Page(s): 96
    Cited by:  Papers (1)
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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty