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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 5 • Date May 2011

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  • Table of contents

    Publication Year: 2011 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2011 , Page(s): C2
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  • A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

    Publication Year: 2011 , Page(s): 849 - 859
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4234 KB) |  | HTML iconHTML  

    A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is - 87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm2. View full abstract»

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  • A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

    Publication Year: 2011 , Page(s): 860 - 867
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    A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-μm CMOS locks in 40 μs and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1° and the phase noise spectral density is -116.8 dBc/Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are -83 dBc and -105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively. View full abstract»

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  • A Low-Power, Process-and- Temperature- Compensated Ring Oscillator With Addition-Based Current Source

    Publication Year: 2011 , Page(s): 868 - 878
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (931 KB) |  | HTML iconHTML  

    The design of a 1.8 GHz 3-stage current-starved ring oscillator with a process- and temperature- compensated current source is presented. Without post-fabrication calibration or off-chip components, the proposed low variation circuit is able to achieve a 65.1% reduction in the normalized standard deviation of its center frequency at room temperature and 85 ppm/ ° C temperature stability with no penalty in the oscillation frequency, the phase noise or the start-up time. Analysis on the impact of transistor scaling indicates that the same circuit topology can be applied to improve variability as feature size scales beyond the current deep submicron technology. Measurements taken on 167 test chips from two different lots fabricated in a standard 90 nm CMOS process show a 3x improvement in frequency variation compared to the baseline case of a conventional current-starved ring oscillator. The power and area for the proposed circuitry is 87 μW and 0.013 mm2 compared to 54 μ W and 0.01 mm 2 in the baseline case. View full abstract»

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  • Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers

    Publication Year: 2011 , Page(s): 879 - 892
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (859 KB) |  | HTML iconHTML  

    It has been shown that an arrangement of four MOS switches and four baseband lowpass impedances can synthesize on-chip high-Q bandpass filters if the switches are driven by proper clock phases. The technique has been successfully utilized in receivers to replace external SAW filters. This paper analyzes performance of these filters in SAW-less receivers against imperfections such as clock phase-noise, thermal noise of switches, second-order non-linearity of switches and clock phase error. Such receivers deal with out-of-band blockers by utilizing on-chip high-Q 4-phase bandpass filters. View full abstract»

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  • Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX

    Publication Year: 2011 , Page(s): 893 - 901
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2070 KB) |  | HTML iconHTML  

    This paper discusses the circuits and system design methodology of a highly-efficient wideband RF polar transmitter (TX) using the envelope-tracking (ET) technique for mobile WiMAX applications. Monolithic power amplifiers (PAs) are designed and fabricated in IBM 0.18 μm SiGe BiCMOS technology, and a linear-assisted switch-mode envelope amplifier is applied to modulate the PA supply voltage to form the core of the RF polar TX. Nonlinearities caused by bandwidth limitation of the envelope amplifier and timing misalignment have been investigated. When driven by WiMAX 64QAM 8.75 MHz signals, the overall PAE of our ET-based polar TX system reaches 30.5% at 17 dBm average output power, while also meeting the stringent WiMAX linearity specs without using any predistortion. When the decresting algorithm using the soft limiter is applied to the baseband, the overall PAE increases to 33%, at the expense of a higher EVM of 4.9%. Based on measurement results, our ET-based polar TX system has demonstrated excellent efficiency with good linearity for high peak-to-average ratio (PAR) broadband signals when compared with the recent literature on state-of-the-arts polar TX designs. View full abstract»

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  • Analysis and Design of Class-E _{3} F and Transmission-Line Class-E _{3} F _{2} Power Amplifiers

    Publication Year: 2011 , Page(s): 902 - 912
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2001 KB) |  | HTML iconHTML  

    In this paper, analysis and synthesis approach for two new variants within the Class-EF power amplifier (PA) family is elaborated. These amplifiers are classified here as Class-E3 F and transmission-line (TL) Class-E 3F 2. The proposed circuits offer means to alleviate some of the major issues faced by existing topologies such as substantial power losses due to the parasitic resistance of the large inductor in the Class-EF load network and deviation from ideal Class-EF operation due to the effect of device output inductance at high frequencies. Both lumped-element and transmission-line load networks for the Class-E 3F PA are described. The load networks of the Class-E3 F and TL Class-E3 F2 amplifier topologies developed in this paper simultaneously satisfy the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Optimum circuit component values are analytically derived and validated by harmonic balance simulations. Trade-offs between circuit figures of merit and component values with some practical limitations being considered are discussed. View full abstract»

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  • All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of -{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}} After One-Point Calibration

    Publication Year: 2011 , Page(s): 913 - 920
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (901 KB) |  | HTML iconHTML  

    To get rid of the heavy burden of aspect ratio tuning, bias adjustment and porting problem among processes in full-custom or mixed-mode design, a fully digital smart temperature sensor realizable with 140 field programmable gate array (FPGA) logic elements was proposed for painless VLSI on-chip integrations. By simply replacing the cyclic delay line with a retriggerable ring oscillator for accuracy enhancement, modifying the gain of time amplifier from fixed to variable for one-point calibration support and adopting a second-order master curve for curvature correction in this paper, the proposed smart temperature sensor can achieve two thirds reduction in circuit size, at least four-fold improvement in power consumption and more than two-fold enhancement in accuracy. To demonstrate the performance under practical process variation, the sensor realized with as few as 48 FPGA logic elements for rapid prototyping was measured over 0°C to 100°C range for 20 test chips from batches spreading over 4 years. The measured inaccuracy is -0.7°C-+0.6°C which is superior to -1.8°C-+2.3°C of its full-custom predecessor with a third-order master curve and five test samples from one single batch. The accuracy is even better than those of full-custom sensors with two-point calibration. The conversion rate is around 4.4 kHz and the power consumption can be reduced to 175 nJ per conversion by increasing the number of delay stages in ring oscillator to 4608. View full abstract»

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  • An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

    Publication Year: 2011 , Page(s): 921 - 934
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1408 KB) |  | HTML iconHTML  

    An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 μm CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 μW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration. View full abstract»

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  • Low Latency GF(2^{m}) Polynomial Basis Multiplier

    Publication Year: 2011 , Page(s): 935 - 946
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (962 KB) |  | HTML iconHTML  

    Finite field GF(2m) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra. Among finite field arithmetic operations, GF(2m) multiplication is of special interest because it is considered the most important building block. This contribution describes a new low latency parallel-in/parallel-out sequential polynomial basis multiplier over GF(2m). For irreducible GF(2m) generating polynomials f(x)=xm+xkt+xkt-1+⋯+xk1+1 with m ≥ 2kt-1, the proposed multiplier has a theoretical latency of 2kt+1 cycles . This latency is the lowest one found in the literature for GF(2m) multipliers. Furthermore, the condition m ≥ 2kt-1 is specially important because the five binary irreducible polynomials recommended by NIST for elliptic curve cryptography (ECC) implementation verify this condition. View full abstract»

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  • Design of Fixed-Width Multipliers With Linear Compensation Function

    Publication Year: 2011 , Page(s): 947 - 960
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3384 KB) |  | HTML iconHTML  

    This paper focuses on fixed-width multipliers with linear compensation function by investigating in detail the effect of coefficients quantization. New fixed-width multiplier topologies, with different accuracy versus hardware complexity trade-off, are obtained by varying the quantization scheme. Two topologies are in particular selected as the most effective ones. The first one is based on a uniform coefficient quantization, while the second topology uses a nonuniform quantization scheme. The novel fixed-width multiplier topologies exhibit better accuracy with respect to previous solutions, close to the theoretical lower bound. View full abstract»

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  • Design of a Low-Power Coprocessor for Mid-Size Vocabulary Speech Recognition Systems

    Publication Year: 2011 , Page(s): 961 - 970
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB) |  | HTML iconHTML  

    Speech recognition systems have gained popularity in consumer electronics. This paper presents a custom-designed coprocessor for output probability calculation (OPC), which is the most computation-intensive processing step in continuous hidden Markov model (CHMM)-based speech recognition algorithms. To save hardware resource and reduce power consumption, a polynomial addition-based method is used to compute add-log instead of the traditional look-up table-based method. In addition, the optimal tradeoff between speech processing delay, energy consumption, and hardware resources is explored for the coprocessor. The proposed coprocessor has been implemented and tested in Xilinx Spartan-3A DSP XC3SD3400A, and also validated using the standard-cell-based approach in IBM 0.13 μm technology. To implement an entire speech recognition system, SAMSUNG S3C44b0X (containing an ARM7) is used as the micro-controller to execute the rest of speech processing. Tested with a 358-state 3-mixture 27-feature 800-word HMM, S3C44b0X operates at 40 MHz and coprocessor at 10 MHz to meet the real-time requirement, and the recognition accuracy is 95.2%. Power consumption of the micro-controller is 10 mW, and that of the coprocessor 15.2 mW. The overall speech recognition system achieves the lowest energy consumption per word recognition among many reported designs. Experiment and analysis show that the speech recognition system based on the proposed coprocessor is especially suitable for mid-size vocabulary (100-1000 words) recognition tasks. View full abstract»

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  • Application-Specific Processor for Piecewise Linear Functions Computation

    Publication Year: 2011 , Page(s): 971 - 981
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1794 KB) |  | HTML iconHTML  

    This paper presents an application specific processor architecture for the calculation of simplicial piecewise linear functions of up to six dimensions with 24-bit wide input words. The architecture, in particular registers and bus connections, is specifically designed for the task of simplicial piecewise linear computation. The parameters of the function are stored in an external 16 MB RAM memory. A proof-of-concept integrated circuit (that achieved first silicon success) was fabricated through MOSIS in a 4 mm × 4 mm 0.5 μm standard CMOS process using an automated design flow based on Synopsys and Cadence tools and the OSU standard cell library. View full abstract»

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  • Radix-8 Booth Encoded Modulo 2 ^{n} -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System

    Publication Year: 2011 , Page(s): 982 - 993
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very-large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2n-1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and power consumption without compromising the system performance. With this precept, a family of radix-8 Booth encoded modulo 2n-1 multipliers, with delay adaptable to the RNS multiplier delay, is proposed. The modulo 2n-1 multiplier delay is made scalable by controlling the word-length of the ripple carry adder, k employed for radix-8 hard multiple generation. Formal criteria for the selection of the adder word-length are established by analyzing the effect of varying k on the timing of multiplier components. It is proven that for a given n, there exist a number of feasible values of k such that the total bias incurred from the partially-redundant partial products can be counteracted by only a single constant binary string. This compensation constant for different valid combinations of n and k can be precomputed at design time using number theoretic properties of modulo 2n-1 arithmetic and hardwired as a partial product to be accumulated in the carry save adder tree. The adaptive delay of the proposed family of multipliers is corroborated by CMOS implementations. In an RNS multiplier, when the critical modulo multiplier delay is significantly greater than the noncritical modulo 2n-1 multiplier delay, k = n and k = n /3 are recommended for n not divisible by three and divisible by three, respectively. Conversely, when this difference diminishes, k is better selected as n /4 and n /6 for n not divisible by three and divisib le by three, respectively. Our synthesis results show that the proposed radix-8 Booth encoded modulo 2n-1 multiplier saves substantial area and power consumption over the radix-4 Booth encoded multiplier in medium to large word-length RNS multiplication. View full abstract»

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  • Exponential H_{\infty } Filter Design for Discrete Time-Delay Stochastic Systems With Markovian Jump Parameters and Missing Measurements

    Publication Year: 2011 , Page(s): 994 - 1007
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (517 KB) |  | HTML iconHTML  

    In this paper, the exponential H filtering problem is studied for discrete time-delay stochastic systems with Markovian jump parameters and missing measurements. The measurement missing phenomenon, which is related to the modes of subsystems, is described in the form of random matrix function and the missing probability of each sensor at every mode is governed by an individual random variable taking values in the interval [0,1] . This description of missing measurements is more general than the existing ones, where the missing probability is described by a Bernoulli distribution white sequence or a certain diagonal matrix. By using Lyapunov method and the properties of conditional mathematical expectation, we propose a novel approach to achieve the delay-dependent exponential stability criterion such that the filtering error system is mean-square exponentially stable and satisfies a prescribed H performance level. Moreover, there is no equation restriction on decay rate. Then, based on the obtained sufficient criterion, the filter matrices can be directly characterized by solving a set of linear matrix inequalities (LMIs). Finally, a numerical example is provided to show the validity of the main result. View full abstract»

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  • Closed-Form Mixed Design of High-Accuracy All-Pass Variable Fractional-Delay Digital Filters

    Publication Year: 2011 , Page(s): 1008 - 1019
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    This paper presents a closed-form method for minimizing the weighted squared error of variable fractional-delay (VFD) of an all-pass VFD digital filter under an equality constraint on its normalized root-mean-squared (NRMS) error of variable frequency response (VFR). The main purpose is to reduce the squared VFD error as much as possible while keeping its NRMS VFR error exactly at a predetermined value. We first prove that the linearized VFR error of an all-pass VFD filter is almost the same as its linearized phase error, and then convert the equality-constrained weighted-least-squares (WLS) design into an unconstrained optimization problem through the minimization of a mixed error function that mixes the weighted squared VFD error and squared VFR error. To reduce the computational complexity, we derive a closed-form mixed error function by utilizing Taylor series expansions of trigonometric functions. Therefore, the error functions can be efficiently computed without discretizing the design parameters (frequency ω and VFD parameter p). The closed-form mixed error function not only reduces the computational complexity, but also speeds up the design process as well guarantees the optimality of the final solution. Furthermore, a two-point search (dichotomous search) scheme is proposed for finding the optimal range p ∈ [pMin,pMax] of the VFD parameter p, and then the subfilter orders are optimized under a given filter complexity constraint (the number of all-pass VFD filter coefficients). This two-stage optimization process utilizes the NRMS VFD error as an error criterion. Design examples and comparisons are given to demonstrate that the closed-form mixed WLS method yields low-complexity all-pass VFD filters with a high-accuracy VFD response but without noticeably degrading its frequency response. View full abstract»

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  • Stochastic Analysis of the Normalized Subband Adaptive Filter Algorithm

    Publication Year: 2011 , Page(s): 1020 - 1033
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3721 KB) |  | HTML iconHTML  

    This paper studies the statistical behavior of the normalized subband adaptive filtering (NSAF) algorithm. An accurate statistical model of the NSAF algorithm is obtained. In the derivation, we focus on Gaussian correlated input signals. By assuming that the analysis filter bank is paraunitary and taking into account the full band adaptation mechanism of the NSAF, expressions for the first and the second moments of the adaptive filter weights are derived without invoking the slow adaptation assumption. In the derivations, several hyperelliptic integrals appear. To tackle those integrals induced by Gaussian correlated inputs, we first give a solution by resorting to the adaptive Lobatto quadrature. By invoking the averaging principle, two other approximation methods, the chi-square method and the partial fraction expansion method, are presented to approximate the statistical model as well. Monte Carlo (MC) simulation results corroborate our predictions. The Lobatto quadrature method achieves a good agreement with the MC simulation results, even for a relatively large step size. Compared with the chi-square method and the partial fraction expansion method, the Lobatto quadrature method gives better performance in terms of predicting the mean square error when the length of the adaptive filters is small to medium. The chi-square approximation method and the partial fraction expansion method give a satisfactory performance with a relatively low computational complexity when the filter length is large. View full abstract»

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  • Silicon-Neuron Design: A Dynamical Systems Approach

    Publication Year: 2011 , Page(s): 1034 - 1043
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB) |  | HTML iconHTML  

    We present an approach to design spiking silicon neurons based on dynamical systems theory. Dynamical systems theory aids in choosing the appropriate level of abstraction, prescribing a neuron model with the desired dynamics while maintaining simplicity. Further, we provide a procedure to transform the prescribed equations into subthreshold current-mode circuits. We present a circuit design example, a positive-feedback integrate-and-fire neuron, fabricated in 0.25-μm CMOS. We analyze and characterize the circuit, and demonstrate that it can be configured to exhibit desired behaviors, including spike-frequency adaptation and two forms of bursting. View full abstract»

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  • True Random Number Generation Via Sampling From Flat Band-Limited Gaussian Processes

    Publication Year: 2011 , Page(s): 1044 - 1051
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    We consider a true random number generator based on regularly sampling a thresholded wide sense stationary Gaussian noise source of which power spectral density is assumed to be flat between two known frequencies and zero everywhere else. We employ per-sample joint entropy of the resulting bit sequence as the main figure of merit and present novel analytical results on the optimum choice of the sampling period that ensures maximal randomness of the resulting bit sequence together with numerical results. In addition, we provide new results that follow from autocorrelation function of the noise source and introduce a new related metric, termed “spectral correlation” to quantify the pairwise dependence among the generated bits. View full abstract»

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  • Limit Set Dichotomy and Convergence of Cooperative Piecewise Linear Neural Networks

    Publication Year: 2011 , Page(s): 1052 - 1062
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    This paper considers a class of nonsymmetric cooperative neural networks (NNs) where the neurons are fully interconnected and the neuron activations are modeled by piecewise linear (PL) functions. The solution semiflow generated by cooperative PLNNs is monotone but, due to the horizontal segments in the neuron activations, is not eventually strongly monotone (ESM). The main result in this paper is that it is possible to prove a peculiar form of the Limit Set Dichotomy for this class of cooperative PLNNs. Such a form is slightly weaker than the standard form valid for ESM semiflows, but this notwithstanding it permits to establish a result on convergence analogous to that valid for ESM semiflows. Namely, for almost every choice of the initial conditions, each solution of a fully interconnected cooperative PLNN converges toward an equilibrium point, depending on the initial conditions, as t → +∞. From a methodological viewpoint, this paper extends some basic techniques and tools valid for ESM semiflows, in order that they can be applied to the monotone semiflows generated by the considered class of cooperative PLNNs. View full abstract»

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  • On Full-Connectivity Properties of Locally Connected Oscillatory Networks

    Publication Year: 2011 , Page(s): 1063 - 1075
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    The latest many-core chip technology advances foster highly parallel computing systems. Consequently, it is crucial to conceive hardware oriented architectures and to realize VLSI platforms, with kilo- or mega-processors, that are able to process and recognize spatial-temporal patterns without breaking them into frames. Oscillatory networks, their archetype being the Turing morphogenesis model, represent a suitable paradigm for processing spatial-temporal time-periodic patterns. In this manuscript we aim at pointing out full-connectivity properties of locally connected oscillatory networks (LCONs) with linear memoryless and space-invariant interactions. In particular, it is analytically shown that LCONs can implement any operators of globally connected networks with linear dynamical interactions, if some suitable components of the oscillator state vector are coupled. The key issue of our results is that the inverse of a banded matrix is almost always full, i.e., almost all of its entries are nonzero. Space-invariant local connectivity allows for hardware realizations with straightforward architectures. View full abstract»

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  • On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator

    Publication Year: 2011 , Page(s): 1076 - 1088
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2862 KB) |  | HTML iconHTML  

    In this paper, a new VLSI implementable Hopf oscillator with dynamic plasticity is proposed for next-generation portable signal processing application. A circuit-realizable piece-wise linear function has been used to govern the frequency adaptation characteristic of the proposed oscillator. Furthermore, a straightforward method is suggested to extract the frequency component of the input signal. Mathematical model of the oscillator is derived and it is shown, using VHDL-AMS model, that despite using a new nonlinear function, the oscillator exhibits the same characteristics and learning behavior as the original one with improved learning time. Subsequently, an equivalent circuit model and transistor level implementation for the oscillator is suggested and the mathematical model is confirmed with system and circuit level simulations. Capability of such oscillator to extract frequency futures without doing explicit signal processing is shown with examples of both synthetic and real-life EMG signals. View full abstract»

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  • Design-Oriented Analysis of Circuits With Equality Constraints

    Publication Year: 2011 , Page(s): 1089 - 1098
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (647 KB) |  | HTML iconHTML  

    This paper presents a design-oriented circuit analysis that is augmented with design constraints. This analysis computes the circuit response and also finds the values of circuit parameters (equal to the number of design specifications) that result in a specified circuit performance. An application of this approach is demonstrated for the periodic steady-state analysis with shooting and finite difference formulations. The new analysis with design equality constraints is several times faster than search-based techniques that employ conventional analysis methods. View full abstract»

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  • Notes on the State Space Realizations of Rational Order Transfer Functions

    Publication Year: 2011 , Page(s): 1099 - 1108
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    In this paper, the concept of minimal state space realization for a fractional order system is defined from the inner dimension point of view. Some basic differences of the minimal realization concept in the fractional and integer order systems are discussed. Five lower bounds are obtained for the inner dimension of a minimal state space realization of a fractional order transfer function. Also, the concept of optimal realization, which can be a helpful concept in practice, is introduced for transfer functions having rational orders. An algorithm is suggested to obtain the optimal realizations of rational order transfer functions. The introduced concept might be used to get minimal realizations of rational order transfer functions. This point is illustrated by presenting some examples. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras