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Electron Devices, IEEE Transactions on

Issue 5 • Date May 2011

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Displaying Results 1 - 25 of 49
  • Table of contents

    Publication Year: 2011 , Page(s): C1 - 1278
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2011 , Page(s): C2
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  • Editorial

    Publication Year: 2011 , Page(s): 1279 - 1280
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  • Reconfigurable CMOS Oscillator Based on Multifrequency AlN Contour-Mode MEMS Resonators

    Publication Year: 2011 , Page(s): 1281 - 1286
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (810 KB) |  | HTML iconHTML  

    This paper reports on the first demonstration of a reconfigurable complementary-metal-oxide-semiconductor (CMOS) oscillator based on microelectromechanical system (MEMS) resonators operating at four different frequencies (268, 483, 690, and 785 MHz). A bank of multifrequency switchable AlN contour-mode MEMS resonators was connected to a single CMOS oscillator circuit that can be configured to selectively operate in four different states with distinct oscillation frequencies. The phase noise (PN) of the reconfigurable oscillator was measured for each of the four different frequencies of operation, showing values between -94 and - 70 dBc/Hz at a 1-kHz offset and PN floor values as low as -165 dBc/Hz at a 1-MHz offset. Jitter values as low as a 114-fs root mean square (integrated 12 kHz-20 MHz) and switching times as fast as 20 μs were measured. This first prototype represents a miniaturized solution (30 times smaller) over commercially available voltage-controlled surface-acoustic-wave oscillators and potentially has the advantage of generating multiple stable frequencies without the need of cumbersome and power-consuming phase-locked-loop circuits. View full abstract»

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  • An Efficient Approach to Include Full-Band Effects in Deterministic Boltzmann Equation Solver Based on High-Order Spherical Harmonics Expansion

    Publication Year: 2011 , Page(s): 1287 - 1294
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    We present an efficient method to include full-band-structure effects for the case of a silicon conduction band in a deterministic Boltzmann equation solver based on the high-order spherical harmonics expansion method. This method employs the exact density of states and the group velocity obtained from band structure calculations, and it eliminates the modulus of the wave vector in the formulation such that an explicit invertible dispersion relation is not required. While the present method does not require additional central-processing-unit time and memory, compared with the analytic band model, the simulation results are significantly improved and in excellent agreement with those from the full-band Monte Carlo simulations and from an approach based on an invertible anisotropic band that matches several moments of the group velocity of the full band structure. View full abstract»

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  • High-Electron-Mobility \hbox {Ge/GeO}_{2} n-MOSFETs With Two-Step Oxidation

    Publication Year: 2011 , Page(s): 1295 - 1301
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    We propose a two-step oxidation with high-pressure oxidation and low-temperature oxygen annealing to form ideal Ge/GeO2 stacks based on thermodynamic and kinetic control. The capacitance-voltage (C-V) characteristics of Ge/GeO2 MISCAPs with two-step oxidation revealed significant improvements of electrical properties, and the interface states density (Dit) estimated with a low-temperature conductance method that was below 1011 eV-1 cm-2 near the midgap. On the basis of our understanding of Ge oxidation, we demonstrated very high electron mobility in Ge n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) that exceeded the universal mobility in Si-MOSFETs. The peak electron mobility in Ge n-MOSFETs with the two-step oxidation was 1100 cm2/V · s in the Al/GeO2/Ge stack. This was achieved by taking care of the Ge/GeO2 channel interface. Since we clarified that mobility was still limited by the remaining extrinsic scattering sources, the present results promise much higher performance Ge complementary metal-oxide-semiconductor. View full abstract»

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  • 25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)

    Publication Year: 2011 , Page(s): 1302 - 1310
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1704 KB) |  | HTML iconHTML  

    Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage (VTH) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low VTH variability nMOSFETs with a Si:C-Si epitaxial channel structure. View full abstract»

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  • A Dual-Channel Ferroelectric-Gate Field-Effect Transistor Enabling nand -Type Memory Characteristics

    Publication Year: 2011 , Page(s): 1311 - 1318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    We demonstrate here an oxide memory (OxiM) transistor as a new type of ferroelectric-gate field-effect transistor (FeFET), provided with a dual (top and bottom) channel, which can memorize channel conductance with a dynamic range exceeding 104. This new transistor consists entirely of the following oxide-based thin films: SrRuO3 (bottom gate electrode); Pb(Zr, Ti)O3 (ferroelectric); ZnO (semiconductor); and SiON (gate insulator). A notable feature of the OxiM transistor is that two types of FET, i.e., a top gate-type thin-film transistor (top-TFT) and a bottom gate-type FeFET (bottom-FeFET), are stacked with a conduction layer of thin ZnO film in common. The channel conductance of the top-TFT and the bottom-FeFET can be controlled independently by the top gate and the bottom gate, respectively. We were successful in fabricating a nand memory circuit using serially connected OxiM transistors. The dual-gate structure allows disturb-free reading. Multivalued data can also be memorized in an OxiM transistor with a retention time of over 3.5 months. View full abstract»

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  • Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

    Publication Year: 2011 , Page(s): 1319 - 1328
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB) |  | HTML iconHTML  

    Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantum-mechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moore's law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metal-oxide-semiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies. View full abstract»

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  • Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity

    Publication Year: 2011 , Page(s): 1329 - 1335
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1225 KB) |  | HTML iconHTML  

    This paper presents vertical-Si-nanowire (SiNW) gate-all-around nonvolatile memory (NVM) devices of two different kinds: junction based and junctionless (JL). Si nanocrystals (SiNCs) and silicon nitride (SiN) are used as trap layers. The devices are fabricated using complementary-metal-oxide-semiconductor-compatible top-down process technology and compared on the bases of improved performance and reduced process complexity. The junction-based 50-nm vertical-SiNW memory device with a SiNC trap layer shows significant performance improvements on program/erase (P/E) speed and windows (3.5 V in 1-ms P/E at +15/-16 V) over a memory cell with a SiN trap layer (1.3 V in 1-ms P/E at +15/-16 V). On the other hand, the JL device with a SiN trap layer, realized on a highly scaled SiNW channel (down to 20 nm), is found to have comparable memory characteristics (3.2 V in 1-ms P/E at +15/-16 V) to a corresponding 20-nm SiNW junction-based cell (2.7 V in 1-ms P/E at +15/-16 V). Despite of that, the absence of junctions reduces process complexity and makes a vertical SiNW a suitable platform for multilevel stacked ultrahigh density memory applications. View full abstract»

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  • Analysis of Carrier Transport in Trigate Si Nanowire MOSFETs

    Publication Year: 2011 , Page(s): 1336 - 1343
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    Trigate Si nanowire (NW) MOSFETs have been fabricated and characterized at temperature between 77 and 300 K in the dark and under light pumping. The NW width W and height H, the gate length Lg, and the gate oxide thickness tox, respectively, were 7-25, 16, 34-52, and 7 nm. The interesting aspects of Si NW MOSFETs with W/Lg = 25 nm /52 nm, 24 nm/34 nm, 7 nm/47 nm, and 10 nm/37 nm measured at low drain voltage are that the drain current exhibited not only inverse temperature dependence in strong accumulation but also clear current plateaus/oscillations near the threshold regime at temperature up to 300 K. Notably, such current plateaus diminished or were invisible in the device of W/Lg = 24 nm/42 nm. The observed current behaviors are inferred from the interplay of quantum interference and intersubband scattering effects. Additional current plateaus due to photogenerated excitons were also observed in the studied devices, evidencing photoexcitation effects on quantum transports through a Si NW. View full abstract»

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  • Electron Trapping in HfAlO High- \kappa Stack for Flash Memory Applications: An Origin of V_{\rm th} Window Closure During Cycling Operations

    Publication Year: 2011 , Page(s): 1344 - 1351
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-κ materials. It is observed in this paper that the electron trapping in high-κ layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-κ layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming. View full abstract»

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  • Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM)

    Publication Year: 2011 , Page(s): 1352 - 1360
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1214 KB) |  | HTML iconHTML  

    A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I-V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the Ag/Ge0.3Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. View full abstract»

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  • Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

    Publication Year: 2011 , Page(s): 1361 - 1370
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1121 KB) |  | HTML iconHTML  

    Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined. View full abstract»

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  • Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

    Publication Year: 2011 , Page(s): 1371 - 1380
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1002 KB) |  | HTML iconHTML  

    The influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field-effect transistors is numerically investigated using a full 3-D quantum transport simulator based on an atomistic sp3d5s* tight-binding model. An interface between silicon and silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function. An oxide layer is modeled in a virtual crystal approximation using fictitious SiO2 atoms. 〈110〉-oriented NWs with different diameters and randomly generated surface configurations are studied. An experimentally observed on-current and threshold voltage are quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental data. View full abstract»

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  • Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

    Publication Year: 2011 , Page(s): 1381 - 1387
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB) |  | HTML iconHTML  

    In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime. View full abstract»

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  • RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

    Publication Year: 2011 , Page(s): 1388 - 1396
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (923 KB) |  | HTML iconHTML  

    This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT. View full abstract»

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  • Experimental Determination of Quantum and Centroid Capacitance in Arsenide–Antimonide Quantum-Well MOSFETs Incorporating Nonparabolicity Effect

    Publication Year: 2011 , Page(s): 1397 - 1403
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1109 KB) |  | HTML iconHTML  

    Experimental gate capacitance (Cg) versus gate voltage data for InAs0.8Sb0.2 quantum-well MOSFET (QW-MOSFET) is analyzed using a physics-based analytical model to obtain the quantum capacitance (CQ) and centroid capacitance (Ccent). The nonparabolic electronic band structure of the InAs0.8Sb0.2 QW is incorporated in the model. The effective mass extracted from Shubnikov-de Haas magnetotransport measurements is in excellent agreement with that extracted from capacitance measurements. Our analysis confirms that in the operational range of InAs0.8Sb0.2 QW-MOSFETs, quantization and nonparabolicity in the QW enhance CQ and Ccent. Our quantitative model also provides an accurate estimate of the various contributing factors toward Cg scaling in future arsenide-antimonide MOSFETs. View full abstract»

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  • Fin- and Island-Isolated AlGaN/GaN HFETs

    Publication Year: 2011 , Page(s): 1404 - 1407
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (505 KB) |  | HTML iconHTML  

    The effects of the variation of the size of isolation mesa of AlGaN/GaN heterojunction field-effect transistors (HFETs) on the device characteristics are presented for the first time. Studies on the direct current and pulsed drain and gate current-voltage characteristics demonstrate a correlation between the pinchoff voltage and the size of the isolation mesa. In this paper, devices fabricated on narrow mesas (i.e., 16 × 40 μm2 fins) and also a device fabricated on an array of very small size mesas (i.e., 16 × 7 μm2 islands) are compared with AlGaN/GaN HFETs of traditionally sized mesas (i.e., 70 × 100 μm2). All these devices show maximum extrinsic gate transconductance greater than 220 mS/mm, whereas the pinchoff voltage is observed to become less negative by reducing the size of the individual mesas. The island-isolated HFETs also enjoy a relatively higher gate transconductance. View full abstract»

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  • Gate-Length Scaling of Ultrashort Metamorphic High-Electron Mobility Transistors With Asymmetrically Recessed Gate Contacts for Millimeter- and Submillimeter-Wave Applications

    Publication Year: 2011 , Page(s): 1408 - 1417
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    We have fabricated and characterized ultrashort gate-length metamorphic high-electron mobility transistors (HEMTs) optimized for high gain performance for millimeter- and submillimeter-wave applications. In this paper, we have systematically evaluated the impact of gate length in the range of 25-50 nm on the device performance by exploring epitaxial layer designs, gate-to-channel distances, and recess widths. The study shows the 25-nm devices underperform their 50-nm counterparts in most of the key figures of merit including output conductance, voltage gain, off-state breakdown, on-state breakdown, and, most importantly, the maximum stable gain. This observation is actually in good agreement with the state-of-the-art results published so far, which indicate that the best overall performance of HEMTs for millimeter- and submillimeter-wave applications comes from devices with gate lengths ranging from 35 to 50 nm. The 25-nm devices, on the other hand, appear to have difficulty in achieving the proper vertical scaling for optimum gain, which is limited by the minimum gate layer thickness necessary to retain good Schottky characteristics. This limitation may eventually be overcome with the adoption of new materials used as the gate layer that can be integrated into the HEMT fabrication process. View full abstract»

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  • AlN/GaN MOS-HEMTs With Thermally Grown \hbox {Al}_{2}\hbox {O}_{3} Passivation

    Publication Year: 2011 , Page(s): 1418 - 1424
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    This paper reports on the processing and characterization of AlN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs). The devices employ thermally grown Al2O3 as a gate dielectric and surface protection and passivation, which is an approach that provides an opportunity to define the ohmic contact areas by wet etching of Al (and optimization of this processing step) prior to the formation of Al2O3 and ohmic metal deposition. The devices also employ a new process technique that significantly suppresses leakage currents on the mesa sidewalls. Fabricated devices exhibited good direct current and radio frequency performance. A high peak current, i.e., ~ 1.5 A/mm, at VGS = +3 V and a current-gain cutoff frequency fT and maximum oscillation frequency fMAX of 50 and 40 GHz, respectively, were obtained for a device with 0.2-μm gate length and 100- μm gate width. Additionally, a robust method for the extraction of the small-signal equivalent circuit suitable for process optimization is described. It relies on intimate process knowledge and device geometry to determine equivalent circuit elements of the fabricated AlN/GaN MOS-HEMTs. View full abstract»

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  • The Multiscale Paradigm in Electronic Device Simulation

    Publication Year: 2011 , Page(s): 1425 - 1432
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    In this paper, we present a framework for the simulation of electronic devices based on a multiscale and multiphysics approach. A formal description is provided that includes both multiscale and multiphysics problems and which can be linked to already established multiscale methods. We present a set of simulations of an AlGaN/GaN nanocolumn based on a multiscale coupling between atomistic descriptions and continuous media models, illustrating the application of such a multiscale approach to electronic device simulation. View full abstract»

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  • Fabrication of Flexible Amorphous-Si Thin-Film Solar Cells on a Parylene Template Using a Direct Separation Process

    Publication Year: 2011 , Page(s): 1433 - 1439
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (658 KB) |  | HTML iconHTML  

    In this paper, we report on the fabrication of flexible amorphous-silicon (a-Si) thin-film solar cells on a parylene template carried by a glass plate without any adhesive. The a-Si thin-film solar cells could be separated directly from the glass carrier after a process temperature of up to 200°C. The a-Si and parylene films were deposited using high-frequency plasma-enhanced chemical vapor deposition and a parylene reactor. The parylene-coated glass plate was treated with thermal annealing and Ar, N2, or O2 plasma. Moreover, SiNx and/or SiOx films were used as barrier layers between the transparent conductive oxide and parylene films. Details of different gas plasmas and barrier effects were investigated in terms of surface morphologies and solar cell characteristics. The a-Si thin-film solar cell on a parylene template with an open-circuit voltage of 0.74 V, a short-circuit current density of 15.69 mA/cm2, a fill factor of 54.98%, and a conversion efficiency of 5.78 % could be obtained. After the 10-mm-radius bending test for 5000 times, the a-Si thin-film solar cells still exhibited a conversion efficiency of 4.94%. These results indicated that a-Si thin-film solar cells on parylene templates have high potential for flexible photovoltaic applications. View full abstract»

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  • High-Performance Flexible a-IGZO TFTs Adopting Stacked Electrodes and Transparent Polyimide-Based Nanocomposite Substrates

    Publication Year: 2011 , Page(s): 1440 - 1446
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    We demonstrated flexible amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) on fully transparent and high-temperature polyimide-based nanocomposite substrates. The flexible nanocomposite substrates were coated on the carrier glass substrates and were debonded after the TFT microfabrication. The adoption of the Ti/IZO stacked electrodes as source/drain/ gain electrodes significantly improved the etching compatibility with other material layers, enabling successful implementation of flexible a-IGZO TFTs onto the transparent nanocomposite substrates by conventional lithographic and etching processes. The flexible a-IGZO TFTs exhibited decent mobility and mechanical bending capability. Field-effect mobility of up to 15.9 cm2/V · s, a subthreshold swing of 0.4 V/dec, a threshold voltage of 0.8 V, and an on/off ratio of >; 108 were extracted from the TFT characteristics. The devices could be bent down to a radius of curvature of 3 mm and yet remained normally functional. Such successful demonstration of flexible oxide TFTs on transparent flexible substrates using fully lithographic and etching processes that are compatible with existing TFT fabrication technologies shall broaden their uses in flexible displays and electronics. View full abstract»

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  • UV and Visible Electroluminescence From a \hbox {Sn:Ga}_{2}\hbox {O}_{3}/\hbox {n}^{+}\hbox {-Si} Heterojunction by Metal–Organic Chemical Vapor Deposition

    Publication Year: 2011 , Page(s): 1447 - 1451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    A Sn-doped Ga2O3 thin film was deposited on a n+-Si substrate by metal-organic chemical vapor deposition. The Ga2O3 film was found to be amorphous-like and exhibited n-type conduction with Sn doping. Room-temperature electroluminescence was clearly observed from the Sn:Ga2O3/n+ -Si diode, including an ultraviolet (UV) emission at ~ 370 nm, a yellow emission at ~ 580 nm, and a red emission at ~ 680 nm. The UV emission is assigned to the transition from SnGa donor to the VGa acceptor, whereas the visible emissions were assigned to be related to the dangling bond defects. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego