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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 4 • Date April 2011

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Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • High-Efficiency Differential RF Front-End for a Gen2 RFID Tag

    Page(s): 189 - 194
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (489 KB) |  | HTML iconHTML  

    This brief proposes the analysis and design of a high-efficiency differential radio-frequency (RF) front-end for electronic-product-code second-generation-compatible RF identification tags. By studying the operating mechanism of an N-stage rectifier using a dynamic compensation technique, we propose a steady-state model to predict its output voltage and power conversion efficiency (PCE). The model gives insight to specify circuit parameters according to different input and load conditions. To compose the RF front-end, the rectifier is designed along with an envelope detector, a voltage regulator, and a backscattering modulator. The RF front-end is implemented in 0.18-μm standard complementary metal-oxide-semiconductor technology with electrically erasable programmable read-only memory. Both simulation and measurement results verify the proposed steady-state model. The maximum PCE of the RF front-end reaches 43% at -17-dBm incident power. View full abstract»

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  • Transmission-Line Class-E Power Amplifier With Extended Maximum Operating Frequency

    Page(s): 195 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (401 KB) |  | HTML iconHTML  

    A novel Class-E power amplifier (PA) topology with transmission-line load network is presented in this brief. When compared with the classic Class-E topology, the new circuit can increase the maximum operating frequency up to 50% higher without trading the other Class-E figures of merit. Neither quarterwave line/massive radio-frequency choke for collector/drain biasing nor additional fundamental-frequency output matching circuit are needed in the proposed PA, thus resulting in a compact design. Closed-form formulations are derived and verified by simulations with practical design limitations carefully taken into consideration and good agreement achieved. View full abstract»

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  • Low-Power Divider Retiming in a 3–4 GHz Fractional-N PLL

    Page(s): 200 - 204
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to fail to lock or to degrade jitter at certain synthesized frequencies. This brief proposes a novel automatic retiming circuit, which mitigates metastability issues and avoids induced noise degradation, without adding a relevant increase in power consumption. A 3-4-GHz PLL implementing this technique has been fabricated in 65-nm CMOS technology. Measured root mean square jitter below 500 fsec over the whole tuning range and added current consumption of 51 μA from a voltage supply of 1.2 V prove the effectiveness of the proposed solution. View full abstract»

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  • A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps

    Page(s): 205 - 209
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    A low-distortion active filter is realized using current-efficient feedforward-compensated operational amplifiers in the integrators and feedforward current injection in the summing amplifier. A third-order elliptic low-pass filter with two possible bandwidth settings of 17 and 8.5 MHz consumes 1.8 mW from a 1.8-V supply and occupies 0.17 mm2 in a 0.18- μm CMOS process. The measured maximum signal-to-noise and distortion ratios at the two bandwidth settings are 50.5 and 52.5 dB, respectively. The corresponding third-order intermodulation intercept points (IIP3) are +28.2 and +30.8 dBm. Automatic tuning is used at the startup to counter process variations and set the bandwidth accurately. View full abstract»

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  • The Study of a Dual-Mode Ring Oscillator

    Page(s): 210 - 214
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    An analytical investigation of a dual-mode ring oscillator is presented. The ring oscillator is designed using a CMOS 0.18-μm technology with differential eight-stage delay cells employing auxiliary input devices. With a proper startup control, the oscillator operates in two different modes covering two different frequency bands. A nonlinear model, along with the linearization method, is used to obtain the transient and steady-state behaviors of the dual-mode ring oscillator. The analytical derivations are verified through HSPICE simulation. The oscillator operates at the frequency bands from 2-5 GHz and from 0.1-2 GHz, respectively. View full abstract»

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  • A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications

    Page(s): 215 - 219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    In this brief, a probabilistic estimation bias (PEB) circuit for a fixed-width two's-complement Booth multiplier is proposed. The proposed PEB circuit is derived from theoretical computation, instead of exhaustive simulations and heuristic compensation strategies that tend to introduce curve-fitting errors and exponential-grown simulation time. Consequently, the proposed PEB circuit provides a smaller area and a lower truncation error compared with existing works. Implemented in an 8 × 8 2-D discrete cosine transform (DCT) core, the DCT core using the proposed PEB Booth multiplier improves the peak signal-to-noise ratio by 17 dB with only a 2% area penalty compared with the direct-truncated method. View full abstract»

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  • Area-Efficient Prefilter Architecture for a CDMA Receiver

    Page(s): 220 - 224
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    This brief proposes an area-efficient memory-based prefilter delay line structure. A prefilter-rake chip-level equalizer is used in a code-division multiple-access receiver to deal with multiple-access interference. A prefilter, which functions as an adaptive filter, has a sparsity property, where the number of taps with nonzero coefficients is much smaller than the number of whole taps. On the basis of the sparsity property, this brief shows how a memory device can be a reasonable candidate for a prefilter delay line. After proposing a scheme to reduce the area of the memory-based delay line, this brief shows that the proposed structure provides less area than a conventional register-based structure in typical industrial cases. View full abstract»

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  • Hardware-Oriented Algorithm for Quaternion-Valued Matrix Decomposition

    Page(s): 225 - 229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (138 KB) |  | HTML iconHTML  

    In this brief, a generalized form for 2-, 4-, and 8-D coordinate rotation digital computer (CORDIC) rotation matrices is suggested, and a novel highly parallel efficient hardware-oriented 8-D octonion CORDIC algorithm for quaternion-valued matrix decomposition is designed and presented. Furthermore, a successful sequence of iterations with guaranteed convergence is determined, and the hardware implementation of this algorithm is considered. Such a processor can be utilized to speed up the Givens rotations and computing the QR and singular-value decomposition processes of a quaternion matrix in a digital signal processor. View full abstract»

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  • Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

    Page(s): 230 - 234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vth's) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vth's are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski was found to be the most suitable definition for predicting the distribution and the write yield. View full abstract»

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  • A Sensor System to Detect Positive and Negative Current-Temperature Dependences

    Page(s): 235 - 239
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB) |  | HTML iconHTML  

    We present a sensor system that determines if the circuit current-temperature (I - T) dependence is positive or negative. While prior temperature sensors can prevent overheating and temperature-induced timing failures in systems with negative I - T dependences, the proposed sensor system can prevent these issues in systems with negative or positive I - T dependences. This capability will become increasingly critical as technology scaling results in positive I - T dependences occurring at near-nominal operating voltages. The fabricated sensor system occupies <; 0.05 mm2, consuming 310 nJ per sample with 20- μs latency in 0.35-μm technology. A process variation compensation unit is presented for the calibration of the temperature sensor, which has a temperature nonlinearity of as low as 0.2%. Sensor functionality is verified over a temperature range of 5°C-80°C and a voltage range of 0.6-3.3 V. The system is shown to achieve this improved functionality while maintaining comparable area, energy, and accuracy with alternative temperature sensor designs. View full abstract»

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  • A New Chaotic Jerk Circuit

    Page(s): 240 - 243
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB) |  | HTML iconHTML  

    Much recent interest has been given to simple chaotic oscillators based on jerk equations that involve a third-time derivative of a single scalar variable. The simplest such equation has yet to be electronically implemented. This paper describes a particularly elegant circuit whose operation is accurately described by a simple variant of that equation in which the requisite nonlinearity is provided by a single diode and for which the analysis is particularly straightforward. View full abstract»

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  • A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique

    Page(s): 244 - 248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    The current accuracy and power efficiency of a boost white light-emitting-diode (WLED) driver are usually design tradeoffs since the power efficiency is inversely proportional to the reference voltage, whereas the current accuracy is proportional to the reference voltage. Traditionally, a boost WLED driver with high current accuracy and high power efficiency demand a large chip area because mismatch decreases with increasing size. This paper proposes an offset calibration technique to improve both current accuracy and power efficiency while keeping the chip area relatively small. An overvoltage protection (OVP) circuit and an overcurrent protection (OCP) circuit prevent the proposed driver from being damaged due to WLED failure. The design is fabricated in a Taiwan Semiconductor Manufacturing Company 0.25-μm 60-V bipolar-CMOS-double-diffused-MOS process. The measurement results show that the current variation is less than 1% when the input voltage and the number of loaded WLEDs are varied in a wide range. The maximum power conversion efficiency is 86.7% at a 5-V input with four loaded WLEDs. The OVP is 58 V, and the OCP is 2 A. View full abstract»

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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope