# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 17 of 17

Publication Year: 2011, Page(s): C1
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2011, Page(s): C2
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• ### Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures

Publication Year: 2011, Page(s):637 - 650
Cited by:  Papers (23)
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Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their performance and flexibility. However, their applications have been restricted to domains based on integer arithmetic since typical CGRAs support only integer arithmetic or logical operations. This paper introduces approaches to mapping applications onto CGRAs supporting both integer and floating-point ... View full abstract»

• ### Automating Logic Transformations With Approximate SPFDs

Publication Year: 2011, Page(s):651 - 664
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During the very large scale integration design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It firs... View full abstract»

• ### Identification of Threshold Functions and Synthesis of Threshold Networks

Publication Year: 2011, Page(s):665 - 677
Cited by:  Papers (21)  |  Patents (3)
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This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This met... View full abstract»

• ### A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design

Publication Year: 2011, Page(s):678 - 690
Cited by:  Papers (29)
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Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new FSM watermarking scheme is proposed by making the authorship information a non-redundant property of the FSM. To overcome the vulnerability to state removal attack and minimize the design overhead, the watermark bits are seamlessly interwoven into the outputs of the existing and free transitions of sta... View full abstract»

• ### Fast Vectorless Power Grid Verification Under an RLC Model

Publication Year: 2011, Page(s):691 - 703
Cited by:  Papers (15)
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As part of early system design, one must verify that the power grid provides the underlying logic circuitry with voltage levels that are within specified ranges. In this paper, we describe a vectorless verification approach that can be applied early in the design process. We adopt an RLC model of the grid in the framework of current constraints that capture uncertainty about circuit details and ac... View full abstract»

• ### Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams

Publication Year: 2011, Page(s):704 - 717
Cited by:  Papers (18)
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We address the problem of computing critical area for open faults (opens) in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is the main computational bottleneck in predicting the yield loss of a very large scale integrated design due to random manufacturing defects. We first model the problem as a geometric graph problem and we sol... View full abstract»

• ### On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees

Publication Year: 2011, Page(s):718 - 731
Cited by:  Papers (5)
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This paper presents an efficient method to solve the obstacle-avoiding rectilinear Steiner tree (OARSMT) problem optimally. Our work is developed based on the GeoSteiner approach in which full Steiner trees (FSTs) are first constructed and then combined into a rectilinear Steiner minimum tree (RSMT). We modify and extend the algorithm to allow obstacles in the routing region. For each routing obst... View full abstract»

• ### Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs

Publication Year: 2011, Page(s):732 - 745
Cited by:  Papers (24)  |  Patents (1)
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Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3-D clock tree design. First, each die needs a complete 2-D clock tree to enable pre-bond tes... View full abstract»

• ### Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous $V_{dd}$, $V_{th}$ Assignments, Gate Sizing, and Placement

Publication Year: 2011, Page(s):746 - 759
Cited by:  Papers (3)
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We present a physical-synthesis based power optimization technique that simultaneously explores the four transforms, multiple Vdd, multiple Vth , cell sizing, and placement, to find a minimum power solution under timing and other constraints. The optimal selection of the design options of all transforms for all cells in the circuit is solved using a new optimization technique called ... View full abstract»

• ### Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Publication Year: 2011, Page(s):760 - 773
Cited by:  Papers (52)  |  Patents (1)
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This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this pape... View full abstract»

• ### Data Encoding Schemes in Networks on Chip

Publication Year: 2011, Page(s):774 - 786
Cited by:  Papers (21)
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An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system-on-chip (SoC) is due to the interconnection system. In fact, as technology shrinks, the power contribute of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of data encoding techniques as a viable way to reduce both power dissipation and energy consumpti... View full abstract»

• ### Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects

Publication Year: 2011, Page(s):787 - 791
Cited by:  Papers (5)
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This letter presents a new method to generate compact stuck-at test sets that offer high defect coverage. The proposed method first selects the most effective patterns from a large N-detect repository, by using a new output deviation-based metric. Then it embeds complete coverage of stuck-at faults within these patterns, and uses the proposed metric to further improve their defect coverage.... View full abstract»

Publication Year: 2011, Page(s): 792
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2011, Page(s): C3
| |PDF (34 KB)
• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

Publication Year: 2011, Page(s): C4
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu