Early Access ArticlesEarly Access articles are new content made available in advance of the final electronic or print versions and result from IEEE's Preprint or Rapid Post processes. Preprint articles are peer-reviewed but not fully edited. Rapid Post articles are peer-reviewed and edited but not paginated. Both these types of Early Access articles are fully citable from the moment they appear in IEEE Xplore.
Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology for last-level embedded caches. It exhibits ultra-high density (3–4X of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS. As the design and fabrication process mature for the STT-MRAM, there is a need to study the various fault mod... View full abstract»
Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells wi... View full abstract»
This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip.
Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM in main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ReRAM cross-point array. However, 1T1R ReRAM array has signi... View full abstract»
Large-scale 3D crossbar arrays can enable both high-density Storage Class Memory (SCM) and novel non-Von Neumann computation. Such arrays require each nonvolatile memory (NVM) element to have its own non-linear Access Device (AD), to pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Typically, power consumption during write, not read marg... View full abstract»
This paper proposes a dual (1R/1W) port spin-orbit torque magnetic random access memory (1R/1W SOT-MRAM) for energy efficient on-chip cache applications. Our proposed dual port memory can alleviate the impact of write latency on system performance by supporting simultaneous read and write accesses. The spin-orbit device leverages the high spin current injection efficiency of spin Hall metal to ach... View full abstract»
It has become increasingly challenging to respect Moore's well-known law in recent years. Energy efficiency and manufacturing constraints are among the main challenges to current integrated circuits today. The energy efficiency issue is mainly due to the high leakage current from the CMOS transistors that are used to build almost all logic devices. As a result, performance is limited to a few giga... View full abstract»
This paper investigates the impact of voltage scaling on energy and performance of STT-MRAM arrays under write access, which is well known to be energy critical. Simple analytical models of energy and delay are introduced to gain an insight into the energy-performance tradeoff at low voltages, and minimum-energy operation. The minimum-energy point is found to lie at voltages that are substantially... View full abstract»
This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early... View full abstract»
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The IEEE Journal on Emerging and Selected Topics in Circuits and Systems publishes special issues covering the entire Field of Interest of the IEEE Circuits and Systems Society and with particular focus on emerging areas.
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Instituto Nacional de Microelectrónica de Sevilla
IMSE-CNM (CSIC/Universidad de Sevilla)