# IEEE Transactions on Components, Packaging and Manufacturing Technology

## Filter Results

Displaying Results 1 - 24 of 24
• ### [Front cover]

Publication Year: 2011, Page(s): C1
| PDF (403 KB)

Publication Year: 2011, Page(s):455 - 456
| PDF (106 KB)
• ### Die Attach Materials for High Temperature Applications: A Review

Publication Year: 2011, Page(s):457 - 478
Cited by:  Papers (108)
| | PDF (3230 KB) | HTML

The need for high power density and high temperature capabilities in today's electronic devices continues to grow. More robust devices with reliable and stable functioning capabilities are needed, for example in aerospace and automotive industries as well as sensor technology. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching s... View full abstract»

• ### Low-Temperature Bonding to 304 Stainless Steel for High-Temperature Electronic Packaging

Publication Year: 2011, Page(s):479 - 485
Cited by:  Papers (2)
| | PDF (921 KB) | HTML

In this paper, silicon (Si) chips were bonded to 304 stainless steel (304 SS) substrates using silver-indium (Ag-In) binary system without any use of flux. 304 SS substrates were also bonded to 304 SS substrates to develop a low-temperature fluxless process to seal two 304 SS parts together. In the bonding design, Ag and In were deposited separately in a layered structure. Various processes and so... View full abstract»

• ### Proposal of Very High Performance and High Density Printed Wiring Board and Its Very High Productivity Manufacturing Processes

Publication Year: 2011, Page(s):486 - 494
| | PDF (1139 KB) | HTML

Copper sputter-deposition by a newly developed technique called rotation magnetron sputtering is introduced for copper seed layer formation on printed wiring boards (PWBs) as an alternative to the electroless copper plating, which requires many complicated process steps as well as an intentional roughness-induced process to obtain practical adhesion capability between the copper and the resin. A r... View full abstract»

• ### Characterization of Lead-Free Solder and Sintered Nano-Silver Die-Attach Layers Using Thermal Impedance

Publication Year: 2011, Page(s):495 - 501
Cited by:  Papers (38)
| | PDF (673 KB) | HTML

Since a die-attach layer has a significant impact on the thermal performance of a power module, its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10 mV/°C), the gate-emitter voltage of an insulated gate bipolar transi... View full abstract»

• ### Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding

Publication Year: 2011, Page(s):502 - 509
Cited by:  Papers (17)
| | PDF (1861 KB) | HTML

Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed. A methodology to measure die shift was developed and applied to create maps of die shift on an 8 inch wafer. A total of 256 dies were embedded in an 8 inch mold compound wafer using compression molding. Thermal and cure... View full abstract»

• ### Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

Publication Year: 2011, Page(s):510 - 518
Cited by:  Papers (5)
| | PDF (1008 KB) | HTML

Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprised of completely of IMC compounds, will fail in a sudden unexpected manner as compared to normal solder joints, which fail in a ductile manner, where c... View full abstract»

• ### A Compact Loop Heat Pipe With Flat Square Evaporator for High Power Chip Cooling

Publication Year: 2011, Page(s):519 - 527
Cited by:  Papers (11)
| | PDF (1387 KB) | HTML

In this paper, systematic experimental and theoretical investigations were carried out on a copper-water compact loop heat pipe with a flat square evaporator having a bottom area of 30 mm × 30 mm. Wick structure inside the evaporator was made of fine copper powder with carefully designed vapor removal channels sintered directly on the substrate. In addition, the design and fabrication of a ... View full abstract»

• ### Analysis of Theoretical Limits of Forced-Air Cooling Using Advanced Composite Materials With High Thermal Conductivities

Publication Year: 2011, Page(s):528 - 535
Cited by:  Papers (14)
| | PDF (1756 KB) | HTML

Cooling systems take a significant portion of the total mass and/or volume of power electronic systems. In order to design a converter with high power density, it is necessary to minimize the converter's cooling system volume for a given maximum tolerable thermal resistance. This paper theoretically investigates whether the cooling system volume can be significantly reduced by employing new advanc... View full abstract»

• ### Development of Single Phase Liquid Cooling Solution for 3-D Silicon Modules

Publication Year: 2011, Page(s):536 - 544
Cited by:  Papers (14)
| | PDF (1544 KB) | HTML

Demand for increased functionalities and the trend in product miniaturization have created new challenges for electronic packaging. The move to 3-D packages combines the benefits of small footprint packages and through-silicon-vias technology to overcome the limitations. However, thermal management of such packages has become the bottleneck as cooling solutions cannot access the intermediate stack... View full abstract»

• ### Size and Material Effects on Flow Boiling Enhancement in Microchannels With Diffusion-Brazed Wire Mesh

Publication Year: 2011, Page(s):545 - 556
| | PDF (1187 KB) | HTML

This paper focuses on flow boiling enhancement in microchannels using a surface enhancement technique based on the diffusion-brazing of a mesh to the channel's inner surface. Both qualitative flow boiling visualization using a high-speed camera and quantitative local variable measurements were carried out. Good agreement was obtained from the qualitative and quantitative results. After validation ... View full abstract»

• ### Low-Cost TO-Can Header for Coaxial Laser Modules in 25-Gbit/s Transmission Applications

Publication Year: 2011, Page(s):557 - 565
Cited by:  Papers (3)
| | PDF (1195 KB) | HTML

A new transistor outline-Can (TO-Can) header for a low-cost coaxial laser module for 25-Gbit/s transmission is proposed and demonstrated using a 3-D full-wave electromagnetic simulation. The simulation result is compared with the measured results of a conventional TO-56 header to verify its applicability. A two-section feedthrough hole is employed, and a wire-over-ground feed lead is introduced to... View full abstract»

• ### Modeling and Optimal Design of Shorting Vias to Suppress Radiated Emission in High-Speed Alternating PCB Planes

Publication Year: 2011, Page(s):566 - 573
Cited by:  Papers (9)
| | PDF (1306 KB) | HTML

An analytical mode analysis of vias in the multilayered printed-circuit-board periphery is developed to suppress the electromagnetic radiation induced by ground bounce. After separating the even and odd modes in alternating planes, the far-field radiation of parallel plates is derived using Huygens' principle. It is mainly contributed by the odd mode excitation, while the even mode sets a lower bo... View full abstract»

• ### An Efficient SPICE-Compatible Cavity Resonant Model for Microstrip Lines

Publication Year: 2011, Page(s):574 - 585
Cited by:  Papers (7)
| | PDF (1393 KB) | HTML

A SPICE-compatible cavity resonant transmission line (CTL) model for a single-ended microstrip line is first presented by reducing 2-D cavity resonator to 1-D cavity resonator. This model has low efficiency since it consists of infinite higher-order components included inductors, capacitors, resistors, and ideal transformers. A modified CTL model is developed by using a fast algorithm to improve t... View full abstract»

• ### A New Isolation Structure of Pogo Pins for Crosstalk Reduction in a Test Socket

Publication Year: 2011, Page(s):586 - 594
Cited by:  Papers (2)  |  Patents (1)
| | PDF (855 KB) | HTML

A new isolation structure is integrated in the test socket to reduce the crosstalk between pogo pins with various pin patterns and different signal to ground (S/G) ratios. It comprises inserted vias to shield the signal coupling and two metal planes to connect the inserted vias with the ground pogo pins. The crosstalk between pogo pins with and without the isolation structure is simulated and inve... View full abstract»

• ### Design of Microstrip-to-Microstrip Via Transition in Multilayered LTCC for Frequencies up to 67 GHz

Publication Year: 2011, Page(s):595 - 601
Cited by:  Papers (17)
| | PDF (811 KB) | HTML

A wide-band microstrip-to-microstrip via transition proposed for connecting an integrated circuit chip and an antenna array on the opposite sides of a multilayered low-temperature co-fired ceramic substrate is investigated in this paper. To facilitate the design, it is decomposed into external and internal segments, which consist of two microstrip-to-via transitions and a multilayered through-hole... View full abstract»

• ### A Systematic Method for the Passivity Enforcement of Delayed Rational Macromodels

Publication Year: 2011, Page(s):602 - 610
Cited by:  Papers (1)
| | PDF (965 KB) | HTML

In this paper, an efficient least squares norm based method for the passivity enforcement of delayed rational macromodels is presented. The least squares norm based method and the energy norm based method are described and compared. A new formulation for the objective function of energy norm type is also derived, which shows that least squares norm and energy norm are mathematically equivalent. Th... View full abstract»

• ### Rework of Lead-Free Area Array Packages Assembled on Ultrathin Flexible Substrates

Publication Year: 2011, Page(s):611 - 621
Cited by:  Papers (1)
| | PDF (1614 KB) | HTML

The introduction of stacking technology has enabled the memory industry to cope with the continuous demand for higher performance and greater capacity. Among other variants of stacking, module-level stacking is gaining steady popularity and acceptance as an option to fulfill this need. One of the approaches for module-level stacking is to fold a double-sided flexible substrate-based assembly aroun... View full abstract»

• ### Shelf-Life Study of Ag/NiNiP-Plated Cu Leadframes Without Anti-Tarnish Coating

Publication Year: 2011, Page(s):622 - 629
Cited by:  Papers (2)
| | PDF (534 KB) | HTML

An Ag spot/full nickel and nickel phosphorus (NiNiP)-plated Cu leadframe without the anti-tarnish layer was used for aluminum wire bonding in power packages. Two periods of shelf-life, namely 7 months and 13 months, of the leadframe were studied in terms of processability (die attachment and wire bonding) and package reliability. It was found that the leadframe with 7-month shelf-life showed posit... View full abstract»

• ### SiC Die Attach Metallurgy and Processes for Applications up to 500 $^{circ}{rm C}$

Publication Year: 2011, Page(s):630 - 639
Cited by:  Papers (9)  |  Patents (3)
| | PDF (2369 KB) | HTML

The challenges of packaging SiC-based electronics for high-temperature applications include their high operating temperatures, wide thermal cycle ranges, and, sometimes, high currents and high voltages. As a result, the selection of metallurgy for high-temperature SiC die attach is crucial to a successful package design, which involves chip metallization, substrate metallization, and die attach al... View full abstract»

Publication Year: 2011, Page(s): 640
| PDF (210 KB)
• ### IEEE Components, Packaging, and Manufacturing Technology Society information for authors

Publication Year: 2011, Page(s): C3
| PDF (21 KB)
• ### IEEE Components, Packaging, and Manufacturing Technology Society Information

Publication Year: 2011, Page(s): C4
| PDF (38 KB)

## Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

## Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University