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IEEE Design & Test of Computers

Issue 2 • Date March-April 2011

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Front cover]

    Publication Year: 2011, Page(s): c2
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  • [Masthead]

    Publication Year: 2011, Page(s): 1
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  • Contents

    Publication Year: 2011, Page(s):2 - 3
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  • Targeting Design, Verification, and Test Challenges

    Publication Year: 2011, Page(s):4 - 5
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  • Customizable Domain-Specific Computing

    Publication Year: 2011, Page(s):6 - 15
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    To meet computing needs and overcome power density limitations, the computing industry has entered the era of parallelization. However, highly parallel, general-purpose computing systems face serious challenges in terms of performance, energy, heat dissipation, space, and cost. We believe that there is significant opportunity to look beyond parallelization and focus on domain-specific customizatio... View full abstract»

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  • Exploring NoC-Based MPSoC Design Space with Power Estimation Models

    Publication Year: 2011, Page(s):16 - 29
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different ... View full abstract»

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  • Low-Power, Resilient Interconnection with Orthogonal Latin Squares

    Publication Year: 2011, Page(s):30 - 39
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy re... View full abstract»

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  • Hybrid Testbench Acceleration for Reducing Communication Overhead

    Publication Year: 2011, Page(s):40 - 51
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (413 KB) | HTML iconHTML

    Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57% hardware overh... View full abstract»

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  • A Metric to Target Small-Delay Defects in Industrial Circuits

    Publication Year: 2011, Page(s):52 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (251 KB) | HTML iconHTML

    Timing-related defects are a major cause of test escapes and field returns for very deep-submicron (VDSM) integrated circuits. Small-delay variations induced by crosstalk, process variations, power supply noise, and resistive opens and shorts can cause timing failures in a design, leading to quality and reliability concerns. This article describes the authors' work with a previously proposed test-... View full abstract»

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  • Synthesizing Multiple Scan Trees to Optimize Test Application Time

    Publication Year: 2011, Page(s):62 - 69
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (211 KB) | HTML iconHTML

    This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application t... View full abstract»

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  • Will hardware and software be codesigned? [review of "A Practical Introduction to Hardware/Software Codesign" (Schaumont, P.R.; 2010)]

    Publication Year: 2011, Page(s):70 - 73
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  • Roads not taken

    Publication Year: 2011, Page(s):74 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB) | HTML iconHTML

    This column examines the considerations that underlie how semiconductor manufacturing technologists determine whether a given technology road is worth pursuing. View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2011, Page(s):76 - 77
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  • CEDA Currents

    Publication Year: 2011, Page(s):78 - 79
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  • Information marches on

    Publication Year: 2011, Page(s): 80
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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c3
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  • [Advertisement - Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty