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IEEE Transactions on Computers

Issue 5 • Date May 2011

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2011, Page(s): c2
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  • State of the Journal

    Publication Year: 2011, Page(s):609 - 613
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  • Hardware Designs for Binary Integer Decimal-Based Rounding

    Publication Year: 2011, Page(s):614 - 627
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2246 KB) | HTML iconHTML

    Decimal floating-point (DFP) arithmetic is becoming increasingly important and specifications for it are included in the revised IEEE 754 standard for floating-point arithmetic (IEEE 754-2008). The binary encoding of DFP numbers specified in IEEE 754-2008 is commonly referred to as Binary-Integer Decimal (BID). BID uses a binary integer to encode the significant, which allows it to leverage existi... View full abstract»

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  • Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder

    Publication Year: 2011, Page(s):628 - 638
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2009 KB) | HTML iconHTML

    The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The discrete wavelet transformation (DWT), central to the signal analysis and important in the JPEG 2000, is quite susceptible to computer-induced errors. The errors can be spread to many output transform coefficients if the DWT is implemented by using lifting scheme. This paper proposes an eff... View full abstract»

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  • FREM: A Fast Restart Mechanism for General Checkpoint/Restart

    Publication Year: 2011, Page(s):639 - 652
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3131 KB) | HTML iconHTML

    As failure rate keeps on increasing in large systems, applications running atop restart more frequently than ever. Existing research on checkpoint/restart mainly focuses on optimizing checkpoint operation, without paying much attention to the restart operation. As a result, application restart latency maybe substantial, which greatly threatens system dependability and performance. To attack the re... View full abstract»

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  • Ozone (O3): An Out-of-Order Flash Memory Controller Architecture

    Publication Year: 2011, Page(s):653 - 666
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2318 KB) | HTML iconHTML

    Ozone (O3) is a flash memory controller that increases the performance of a flash storage system by executing multiple flash operations out of order. In the O3 flash controller, data dependencies are the only ordering constraints on the execution of multiple flash operations. This allows O3 to exploit the multichip parallelism inherent in flash memory much more effectively than interleaving. The O... View full abstract»

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  • Exploiting Heterogeneity in P2P Video Streaming

    Publication Year: 2011, Page(s):667 - 679
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1984 KB) | HTML iconHTML

    In this paper, we investigate the impact of peer bandwidth heterogeneity on the performance of a mesh-based P2P system for live streaming. We show that bandwidth heterogeneity constitutes an important resource for P2P live streaming systems. Indeed, by effectively exploiting it, the overall performance of the system is significantly improved. This requires the adoption of smart schemes for both th... View full abstract»

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  • Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs

    Publication Year: 2011, Page(s):680 - 692
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1648 KB) | HTML iconHTML

    Area-time efficient custom instructions are desirable for maximizing the performance of reconfigurable processors. Existing data path merging techniques based on resource sharing can be deployed to improve area efficiency of custom instructions. However, these techniques lead to large increase in the critical path delay. In this paper, we propose a novel strategy that takes into account the archit... View full abstract»

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  • Multiprefix Trie: A New Data Structure for Designing Dynamic Router-Tables

    Publication Year: 2011, Page(s):693 - 706
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4425 KB) | HTML iconHTML

    IP lookup affects the speed of an incoming packet and the time required to determine which output port the packet should be sent to; hence, it plays an important role in the design of router-tables. In this paper, we propose a new data structure, called a multiprefix trie, for use in designing dynamic router-tables. One key feature of our data structure is that each node can store more than one pr... View full abstract»

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  • Energy-Efficient Real-Time Multicast Routing in Mobile Ad Hoc Networks

    Publication Year: 2011, Page(s):707 - 722
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3363 KB) | HTML iconHTML

    In this paper, we present Multicasting through Time Reservation using Adaptive Control for Energy efficiency (MC--TRACE), an energy-efficient real-time data multicasting architecture for mobile ad hoc networks. MC-TRACE is a cross-layer design, where the medium access control layer functionality and the network layer functionality are performed by a single integrated layer. The basic design philos... View full abstract»

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  • Toward Advocacy-Free Evaluation of Packet Classification Algorithms

    Publication Year: 2011, Page(s):723 - 733
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (654 KB) | HTML iconHTML

    Understanding the real performance of a proposed algorithm is a basic requirement for both algorithm designers and implementers. However, this is sometimes difficult to achieve. Each new algorithm published is evaluated from different perspectives and based on different assumptions. Without a common ground, it is almost impossible to compare different algorithms directly. Choosing an incompetent a... View full abstract»

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  • Counterexample-Guided Assume-Guarantee Synthesis through Learning

    Publication Year: 2011, Page(s):734 - 750
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4719 KB) | HTML iconHTML Multimedia Media

    Assume-guarantee reasoning (AGR) is a promising compositional verification technique that can address the state space explosion problem associated with model checking. Since the construction of assumptions usually requires nontrivial human efforts, a framework was already proposed for generating assumptions automatically using the L* algorithm. However, if the framework shows that a system model d... View full abstract»

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  • Stay Connected with the IEEE Computer Society [advertisement]

    Publication Year: 2011, Page(s): 751
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  • Distinguish yourself with the CSDP [advertisement]

    Publication Year: 2011, Page(s): 752
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  • TC Information for authors

    Publication Year: 2011, Page(s): c3
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  • [Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org