Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Embedded Systems Letters, IEEE

Issue 1 • Date March 2011

Filter Results

Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2011 , Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (66 KB)  
    Freely Available from IEEE
  • IEEE Embedded Systems Letters publication information

    Publication Year: 2011 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    Due to the high computational complexity of discrete cosine transform (DCT) computation, prediction of zero quantized DCT (ZQDCT) coefficients has been extensively studied to reduce the computational complexity of DCT computation. In this letter, we propose a reconfigurable architecture to support ZQDCT computation. Twelve different modes of DCT computations including zonal coding, multiblock processing, and parallel-sequential stage mode can be performed using proposed architecture. We develop a hybrid model-based quality priority algorithm to reduce power consumption, required hardware resources, and computation time with a small quality degradation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Low-Overhead Partition-Oriented ERfair Scheduler for Hard Real-Time Embedded Systems

    Publication Year: 2011 , Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (149 KB) |  | HTML iconHTML  

    This letter presents partition-oriented ERfair scheduler (POES), a low-overhead proportional fair scheduler for hard real-time multiprocessor embedded systems. POES achieves lower overheads using an online partitioning/merging mechanism that retains the optimal schedulability of a fully global scheduler by merging processor groups as resources become critical while using partitioning for fast scheduling at other times. The principal objective is to remain only just as global at any given instant of time as is necessary to maintain ERfair schedulability of the system throughout the schedule length. Experimental results reveal that POES incurs almost no migrations at low workloads and achieves up to 32 times reduction in the number of migrations suffered with respect to the global ERfair scheduler on a set of two to 16 processors even when the average system load is as high as 85%. Theoretical analysis proves that POES typically has the same amortized complexity as that of the global ERfair algorithm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Process Algebra as a Common Framework for Hardware/Software Coverification

    Publication Year: 2011 , Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (163 KB) |  | HTML iconHTML  

    This letter presents the practical issues concerning late and insufficient verification of low-level software on hardware platforms developed by our industrial partner. To overcome these issues, we propose a coverification platform based on process algebra. The descriptions of hardware and software, and their interface are translated into a common process-algebraic platform, and formal verification techniques are used to check the conformance of the two descriptions. We present the results of our first attempt towards this goal, discuss the lessons learned, and present the road-map for future research. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff

    Publication Year: 2011 , Page(s): 13 - 15
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (71 KB) |  | HTML iconHTML  

    The need to improve nonvolatile memories reliability in embedded systems is a key design concern. We here propose a methodology, managed by the memory controller, that optimizes the data reliability at the physical level for critical data whereas exploiting the transaction performances for noncritical data. The reliability-performance tradeoff is obtained by partitioning the memory addressable space in different functional blocks, each on written by means of a specific optimized writing algorithm. The method feasibility is demonstrated by a case study exploiting phase change memories (PCMs) features. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallelism, Performance, and Energy-Efficiency Tradeoffs for In Situ Sensor Data Processing

    Publication Year: 2011 , Page(s): 16 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    The in situ processing of vast amounts of data, available intermittently in networks of sensors, motivates investigation of means for achieving high performance when required, but ultralow-power dissipation when idle. One approach is the use of embedded multiprocessor systems, leading to tradeoffs between parallelism, performance, energy-efficiency, and cost. To evaluate these tradeoffs, and to gain insight for future system designs, this letter presents the design, implementation, and evaluation of a miniature, energy-scalable, 24-processor module, L24, for compute-intensive in situ sensor data processing tasks. The platform provides idle power dissipation over an order of magnitude lower than systems employing a monolithic processor of equivalent performance, while dynamic power dissipation remains competitive. Taking into account both application computation and interprocessor communication demands, it is shown that there may exist an optimum operating voltage that minimizes either time-to-solution, energy usage, or the energy-delay product. This optimum operating point is formulated analytically, calibrated with system measurements and instruction-level microarchitectural simulation, and evaluated for the hardware platform and application presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

    Publication Year: 2011 , Page(s): 20 - 23
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    The design and implementation of a lossless compression system for hyperspectral images on a processor-plus-field-programmable gate array (FPGA)-based embedded platform. Software execution time of compression algorithm was profiled first to conclude the decision of accelerating the most time consuming interband prediction module by hardware realization. Efficient algorithm to hardware mapping led to a high throughput accelerator design in FPGA capable of processing 16.5 M pixels/s. A set of optimization techniques were applied systematically to enhance the overall system performance. These include a hierarchical memory access scheme to resolve the bus bandwidth limitation, DMA assisted data transfers to shorten the hardware/software (HW/SW) communication, and various coding style and compiler options to optimize the software execution. The final result shows a 21 speed-up compared to a purely software implementation and the performance was actually bounded by the software section in realizing an entropy coder. A 27 speed-up can be achieved if a simplified coder is used. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Dynamic Resource Management and Scheduling Environment for Embedded Multimedia and Communications Platforms

    Publication Year: 2011 , Page(s): 24 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    We present a framework, OpenCLosE, for dynamic resource management and scheduling of applications written in open compute language (OpenCL) for heterogeneous multimedia and graphics platforms, such as those found in multimedia smartphones and automotive infotainment clusters. We describe the design of a resource manager and master scheduler for the OpenCLosE environment, that allows efficient realization of multiple applications within a multitasked platform. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Kleene Algebra of Tagged System Actors

    Publication Year: 2011 , Page(s): 28 - 31
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB) |  | HTML iconHTML  

    The tagged signal model (TSM) is a formal framework for modeling heterogeneous embedded systems. In the present work, we provide a representation of tagged systems using the semantics of Kleene algebra. Such an algebraic representation facilitates the usage of standard off-the-shelf theorem provers for reasoning about such systems for both behavioral verification through equivalence checking and property verification. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Managing Battery and Supercapacitor Resources for Real-Time Sporadic Workloads

    Publication Year: 2011 , Page(s): 32 - 36
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    Batteries and supercapacitors are complementary: batteries have a high energy-to-weight ratio but are limited in the power levels they can support; supercapacitors can provide high levels of power while they have a much lower energy-to-weight ratio. A battery-supercapacitor duo can therefore prove useful in embedded systems serving sporadic, energy-intensive, tasks: the battery charges the capacitor at a low, fairly steady, rate which maximizes the energy that can be drawn from it, while the supercapacitor satisfies the impulse power demands of the application. In this letter, we characterize such energy sources by means of two performance measures: expected time before the first task failure and the fraction of tasks that fail before the battery dies. or the case of rare (but energy-intensive) sporadic tasks, we present semi-Markov models to evaluate these measures. For more frequent task arrivals, we provide simulation results. This letter demonstrates the impact of various parameters on our performance measures: power draw, capacitor sizing, and the battery rest scheduling policy. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lazy Versus Eager Conflict Detection in Software Transactional Memory: A Real-Time Schedulability Perspective

    Publication Year: 2011 , Page(s): 37 - 41
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    Transactional memory is a mechanism of controlling access to shared resources in concurrent programs. Though originally implemented in hardware, software implementations of transactional memory are now available as library extensions in all major programming language. Lately, variants of software transactional memory (STM) with real-time support have been presented. The conflict detection policy used in STM, which can be of lazy or eager type, determines the point at which transactions are aborted. The conflict detection policy can have a significant effect on the schedulability of tasks sharing common resources. Using an abstract model, we present a real-time scheduling perspective analysis of lazy and eager conflict detection policies used in STM. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Energy-Efficient Heterogeneous System for Embedded Learning and Classification

    Publication Year: 2011 , Page(s): 42 - 45
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    Embedded learning applications in automobiles, surveillance, robotics, and defense are computationally intensive, and process large amounts of real-time data. Systems for such workloads have to balance stringent performance constraints within limited power budgets. High performance computer processing units (CPUs) and graphics processing units (GPUs) cannot be used in an embedded platform due to power issues. In this letter, we propose a low power heterogeneous system consisting of an Atom processor supported by multiple accelerators that target these workloads, and seek to find if such a system can satisfy performance requirements in an energy-efficient manner. We build our low-power system using an Atom processor, an ION, a GPU, and a field-programmable gate array (FPGA)-based custom accelerator, and study its performance and power characteristics using four representative workloads. With such a system, we show an energy improvement of 42-85% over a server comprising a 2.27 GHz quadcore Xeon coupled to a 1.3 GHz 240 core Tesla GPU. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models

    Publication Year: 2011 , Page(s): 46 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (157 KB) |  | HTML iconHTML  

    SystemC is a widely used electronic system-level (ESL) design language that can be used to model both hardware and software at different stages of system design. There has been a lot of research on behavior synthesis of hardware from SystemC, but relatively little work on synthesizing embedded software for SystemC designs. In this letter, we present an approach to automatic software synthesis from SystemC-based on coroutines instead of the traditional approaches based on real-time operating system (RTOS) threads. Performance evaluation results on some realistic applications show that our approach results in impressive reduction of runtime overheads compared to the thread-based approaches. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Call for Nomination New EIC of IEEE Embedded Systems Letters

    Publication Year: 2011 , Page(s): 50
    Save to Project icon | Request Permissions | PDF file iconPDF (103 KB)  
    Freely Available from IEEE
  • 19th international conference on very large scale integration

    Publication Year: 2011 , Page(s): 51
    Save to Project icon | Request Permissions | PDF file iconPDF (573 KB)  
    Freely Available from IEEE
  • Advertisement - Have you visited lately? www.ieee.org

    Publication Year: 2011 , Page(s): 52
    Save to Project icon | Request Permissions | PDF file iconPDF (210 KB)  
    Freely Available from IEEE
  • IEEE Embedded Systems Letters Information for authors

    Publication Year: 2011 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (34 KB)  
    Freely Available from IEEE
  • Blank page [back cover]

    Publication Year: 2011 , Page(s): C4
    Save to Project icon | Request Permissions | PDF file iconPDF (5 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo