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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 3 • Date March 2011

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Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • RF Front-End Concept and Implementation for Direct Sampling of Multiband Signals

    Page(s): 129 - 133
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    The placement of the analog-to-digital converter as near the antenna as possible is a key issue in the software-defined radio receiver design. Direct sampling of the incoming filtered signal is a compact solution enabling channel simultaneity. In this brief, in the context of evenly spaced equal-bandwidth multiband systems, sufficient conditions for the channel allocation assuring that the minimum sub-Nyquist sampling frequency does not imply aliasing are provided. Subsequently, as a validation example, the design of a minimum-sampling-frequency acquisition system for quad-band applications within a ultrawideband frequency range is shown. Moreover, an innovative solution for its radio-frequency front end, basically consisting of a signal-interference multiband bandpass filter, is reported. Experimental results of the built microstrip-filter prototype for the proposed 1-3-GHz-range quad-band system are also given. View full abstract»

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  • A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA

    Page(s): 134 - 138
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    This brief presents the design and the implementation of a dual-band radio-frequency (RF) front end for global navigation satellite system (GNSS) receivers. The dual-band RF front end is composed of a pseudo-differential low-noise amplifier (LNA), down-conversion mixers, and programmable gain amplifiers (PGAs), and can be configured to operate at 1.2 and 1.57 GHz, respectively. The pseudo-differential LNA incorporates an active single-ended-to-differential conversion using capacitive coupling compensation for an improved phase and amplitude imbalance. The high-linearity PGA has a tunable gain range of 18 dB with a 6-dB gain step and a 0.2-dB gain ripple across a 30-MHz band width. The proposed RF front end achieves a maximum voltage gain of 68/65 dB, a noise figure of 2.4/2.6 dB, and an input-referred 1-dB compression point of -42/-39 dBm at the 1.2-/1.57-GHz bands. The receiver draws 10 mA from a 1.8-V power supply. The RF front end is implemented in a 0.18-μm CMOS process, occupying a die area of 1.0 × 0.5 mm2. View full abstract»

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  • A Noise Filtering Technique for Fractional- N Frequency Synthesizers

    Page(s): 139 - 143
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (490 KB) |  | HTML iconHTML  

    A noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order delta-sigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metal-oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz. View full abstract»

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  • High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers

    Page(s): 144 - 148
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    A new design technique that improves operating speed of true single-phase clock-based (TSPC) prescalers is presented. We implement dual-modulus prescalers without using any extra logic gates by exploiting the behavior of the second branch in a TSPC flip-flop. The proposed design technique is applied to ÷2/3 and ÷3/4 prescalers, and their performances are compared with previous work. Implemented in a 130-nm CMOS technology and compared at same process-voltage-temperature conditions, the maximum speed of the ÷2/3 prescaler reaches 88% of the maximum operating frequency of a single TSPC flip-flop, and the ÷3/4 prescaler reaches 75%. In addition, the proposed divide-by-3 prescaler is able to work almost at the speed of the single TSPC flip-flop. A frequency divider that provides dividing ratios of 7, 8, and 9 is implemented as a part of a 3.4-5-GHz integer- N phase-locked loop in a 130-nm CMOS technology. Simulation and measurement results demonstrate high-speed, low-power, and multiple division ratio capabilities of the proposed technique. View full abstract»

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  • Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

    Page(s): 149 - 153
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfrequency band is changed, an overlap region between subfrequency bands causes a large phase error and cycle-to-cycle jitter in an output clock. The proposed BISC circuit can reduce this problem; thus, it is very suitable for a low-power all-digital phase-locked loop design in system-on-a-chip applications. The proposed DCO, implemented with a standard performance 65-nm complementary metal-oxide-semiconductor process, can output frequency ranges from 47.8 to 538.7 MHz. The total power consumption of the DCO with a calibration circuit is 0.142 mW at 58.7 MHz and 0.205 mW at 481.6 MHz. View full abstract»

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  • Phase Noise Simulation in Analog Mixed Signal Circuits: An Application to Pulse Energy Oscillators

    Page(s): 154 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    Noise simulation of oscillators modeled in an analog mixed signal environment is challenging since both conventional steady-state simulation methods, such as shooting and harmonic balance ones, cannot be used. This brief proposes an improved approach based on saltation matrices and an extended formulation that considers the registers of the digital part of the circuit as state variables to determine the steady-state solution and phase noise. The proposed approach allows the correct computation of the fundamental matrix evaluated on the steady-state solution and therefore of the left eigenfunctions that are a key aspect in determining phase noise by exploiting the variational model of the oscillator and Floquet theory. The proposed approach is applied to compute the phase noise of an archetype circuit that implements an energy-restore pulsed oscillator. In these oscillators, the energy lost by the tank is refilled at peculiar time instants determined by a digital controller to maximize efficiency and minimize effects due to flicker noise sources. View full abstract»

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  • Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

    Page(s): 159 - 163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    A sixth-order low-pass transconductor-C filter with a very wide tuning range (fc = 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single-stage folded cascode transconductor is employed to implement the proposed filter. A modified biquadratic topology is introduced to improve linearity performance of the filter over its tuning range. Power consumption of the filter scales linearly with cutoff frequency (60 pW/Hz/pole). Implemented in 0.18-μm complementary metal-oxide-semiconductor technology, the filter exhibits relatively constant noise and linearity performance over its entire tuning range and occupies a silicon area of 0.16 mm2 (0.027 mm2/pole). View full abstract»

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  • 12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation

    Page(s): 164 - 168
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (553 KB) |  | HTML iconHTML  

    This brief presents a monolithic 1.8-V 0.18-μm CMOS temperature-compensated voltage-to-frequency converter for sensor read-out interfaces in wireless sensor network applications. Measurement results show that the proposed converter features are suitable for an output frequency span of 2 MHz with an input voltage range of 0.1-1.6 V. This converter presents a relative error below 4.8% and a linearity error below 0.017% (i.e., 12 b) over the whole frequency span for a range of ( -40°C, + 85°C). Power consumption is 0.423 mW (20 nW in sleep mode), and it occupies an active area of 137 μm x 100 μm. View full abstract»

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  • A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

    Page(s): 169 - 173
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (538 KB) |  | HTML iconHTML  

    In this brief, we present a time-to-digital converter (TDC) in which a single interpolator is used to improve the resolution by time stretching. The interpolator is based on a triple-slope conversion. Without slowing down the measured event, this approach extensively reduces the chip area and the corresponding power consumption, as compared with the prior arts with two parallel time interpolators. A prototype was designed and fabricated in a 0.35- μm CMOS digital process, and its core area merely occupies 0.126 mm2. Measurements show that our TDC achieves a resolution of 357 ps while consuming 1.22 mW with a 2.5-V supply. The dynamic range of the TDC exceeds 1.46 μs. The measurement rate can achieve above 400 kS/s. View full abstract»

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  • Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications

    Page(s): 174 - 178
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    A dynamic bias-current boosting technique that concurrently enables ultralow-power operation and fast-transient behavior is presented in this brief. It is applied to an ultralow-power output-capacitor-free low-dropout regulator (LDO) to demonstrate the bandwidth extension provided during the transient periods. The proposed LDO is capable of providing 50 mA of output current with a minimum dropout voltage of 0.1 V. The ultralow-power LDO is implemented in a commercial 0.13-μm CMOS process, with power consumption of 1.20 μW only. Experimental results verify that both the load- and line-transient responses of the proposed LDO are significantly improved, and the settling times during load and line transients are shortened by as much as 33 and 3 times, respectively. View full abstract»

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  • New Approach to Realize Fractional Power in z -Domain at Low Frequency

    Page(s): 179 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    In this brief, modifications of the Schneider operator and the Al-Alaoui-Schneider-Kaneshige-Groutage rule have been explored for the improved performance of the fractional-order differentiator (FOD) in the low-frequency range. The FOD models are obtained using continued-fraction expansion (CFE), and it is observed that the magnitude responses obtained using the CFE outperform the results of the discretizations of FODs based on existing first-order and higher order s-to-z transformations in the low-frequency range. The phase responses of the FOD models show a linear response over a part of the low-frequency ranges that can be used for various applications. MATLAB simulation results have been presented to validate the effectiveness of the proposed work. These models can be used for hardware realizations of fractional-order systems. View full abstract»

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  • PID-Based Bit Allocation Strategy for H.264/AVC Rate Control

    Page(s): 184 - 188
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    To achieve the best visual quality under the minimum bit rate and the limited buffer size, the rate control allocates appropriate and smooth bits to each frame. This brief proposes an effective bit-allocation strategy for the H.264/Advanced Video Coding rate control. Based on the different characteristics of intraframes and interframes, we introduce the different bit-allocation approaches for them, respectively. A proportional-integer-derivative controller is adopted to minimize the deviation between the target buffer level and the current buffer fullness. To avoid buffer overflow or underflow, a novel setting method for the bit-allocation boundary is presented. Experimental results demonstrate that the proposed bit allocation strategy achieves smooth target bits while better buffer control and visual quality are derived. View full abstract»

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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope