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IEEE Transactions on Computers

Issue 4 • April 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2011, Page(s): c2
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  • A Brief History of the IEEE Transactions on Computers

    Publication Year: 2011, Page(s): 449
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  • Special Section on Chips and Architectures For Emerging Technologies and Applications 
  • Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications

    Publication Year: 2011, Page(s):450 - 451
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  • Exploring the Potential of Threshold Logic for Cryptography-Related Operations

    Publication Year: 2011, Page(s):452 - 462
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1456 KB) | HTML iconHTML

    Motivated by the emerging interest in new VLSI processes and technologies, such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), this paper explores the application of the non-Boolean computational paradigms enabled by such new technologies. In particular, we consider Threshold Logic functions, directly implemen... View full abstract»

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  • 3D Integration of CMOL Structures for FPGA Applications

    Publication Year: 2011, Page(s):463 - 471
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1122 KB) | HTML iconHTML

    In this paper, a novel 3D CMOS nanohybrid technology, 3D CMOL, is introduced to establish FPGA chips. By combining two leading technologies, hybrid CMOS/nanoelectronic circuit (CMOL) and 3D integration, 3D CMOL can provide a feasible and more efficient fabrication/assembly process than the existing 2D CMOL. Furthermore, 3D CMOL FPGA implements circuits in three dimensions so that it can increase t... View full abstract»

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  • Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters

    Publication Year: 2011, Page(s):472 - 483
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2301 KB) | HTML iconHTML

    Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing coherence protocols in hardware, an approach with some design complexity, hardware costs, and restrictions on interconnect behavior. However, for some memory consistency models, an alternative is to enforce coherence in the softwa... View full abstract»

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  • Compressing Cache State for Postsilicon Processor Debug

    Publication Year: 2011, Page(s):484 - 497
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5122 KB) | HTML iconHTML

    During postsilicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyser. In order to reduce the transfer time and save expensive logic analyser memory, we propose to... View full abstract»

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  • Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses

    Publication Year: 2011, Page(s):498 - 507
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2281 KB) | HTML iconHTML

    While a large body of work on output unknown (X) tolerance exists, to the best of the authors' knowledge, no study is provided in the literature which explores the trade-off between X density and compression of circuit stimuli without reducing fault coverage. To this end, we introduce an architectural and algorithmic framework through which we explore this trade-off, the findings of which we discu... View full abstract»

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  • Dynamic Fault Tolerance in Fat Trees

    Publication Year: 2011, Page(s):508 - 525
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2233 KB) | HTML iconHTML Multimedia Media

    Fat trees are a very common communication architecture in current large-scale parallel computers. The probability of failure in these systems increases with the number of components. We present a routing method for deterministically and adaptively routed fat trees, applicable to both distributed and source routing, that is able to handle several concurrent faults and that transparently returns to ... View full abstract»

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  • Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse

    Publication Year: 2011, Page(s):526 - 537
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3055 KB) | HTML iconHTML

    This paper presents a study on macro data load, a novel mechanism to increase the amount of loaded data reuse within a processor. A macro data load brings into the processor a maximum-width data the cache port allows. In a 64-bit processor, for example, a byte load will bring a full 64-bit data from cache and save it in an internal hardware structure, while using for itself only the specified byte... View full abstract»

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  • Reconfigurable Multiagent Embedded Control Systems: From Modeling to Implementation

    Publication Year: 2011, Page(s):538 - 551
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2959 KB) | HTML iconHTML

    The paper deals with reconfigurable embedded control systems following different component-based technologies and/or Architecture Description Languages used today in industry. We define a Control Component as a software unit to support control tasks of the system, which is assumed to be a network of components with precedence constraints. We define an agent-based architecture to handle automatic r... View full abstract»

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  • Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling

    Publication Year: 2011, Page(s):552 - 564
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2199 KB) | HTML iconHTML

    Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consumer in this environment. This paper proposes a technique for reducing memory energy consumption using virtual machine scheduling in multicore systems. We devise several heuristic scheduling algorithms by using a memory powe... View full abstract»

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  • Signature Tree Generation for Polymorphic Worms

    Publication Year: 2011, Page(s):565 - 579
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2102 KB) | HTML iconHTML

    Network-based signature generation (NSG) has been proposed as a way to automatically and quickly generate accurate signatures for worms, especially polymorphic worms. In this paper, we propose a new NSG system-PolyTree, to defend against polymorphic worms. We observe that signatures from worms and their variants are relevant and a tree structure can properly reflect their familial resemblance. Hen... View full abstract»

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  • Efficient and Strategyproof Spectrum Allocations in Multichannel Wireless Networks

    Publication Year: 2011, Page(s):580 - 593
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (511 KB) | HTML iconHTML

    In this paper, we study the spectrum assignment problem for wireless access networks. We assume that each secondary user will bid a certain value for exclusive usage of some spectrum channels for a certain time period or for a certain time duration. A secondary user may also require the exclusive usage of a subset of channels, or require the exclusive usage of a certain number of channels. Thus, s... View full abstract»

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  • A Hybrid Algorithm of Backward Hashing and Automaton Tracking for Virus Scanning

    Publication Year: 2011, Page(s):594 - 601
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1263 KB) | HTML iconHTML

    Virus scanning involves computationally intensive string matching against a large number of signatures of different characteristics. Matching a variety of signatures challenges the selection of matching algorithms, as each approach has better performance than others for different signature characteristics. We propose a hybrid approach that partitions the signatures into long and short ones in the ... View full abstract»

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  • Low Space Complexity Multiplication over Binary Fields with Dickson Polynomial Representation

    Publication Year: 2011, Page(s):602 - 607
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1254 KB) | HTML iconHTML

    We study Dickson bases for binary field representation. Such a representation seems interesting when no optimal normal basis exists for the field. We express the product of two field elements as Toeplitz or Hankel matrix-vector products. This provides a parallel multiplier which is subquadratic in space and logarithmic in time. Using the matrix-vector formulation of the field multiplication, we al... View full abstract»

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  • Distinguish yourself with the CSDP [advertisement]

    Publication Year: 2011, Page(s): 608
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  • TC Information for authors

    Publication Year: 2011, Page(s): c3
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  • [Back cover]

    Publication Year: 2011, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org